國興 鄭 的照片

查看斯高帕斯 (Scopus) 概要

鄭 國興

教授

按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1991 …2023

每年研究成果

篩選
會議論文篇章

搜尋結果

  • 2004

    64-bit low threshold voltage high-speed conditional carry adder by complementary pass-transistor logic

    Cheng, K. H., Cheng, S. W. & Liao, C. Y., 2004, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. Smailagic, A. & Bayoumi, M. (編輯). p. 233-236 4 p. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • A 2.2 GHz programmable DLL-based frequency multiplier for SOC applications

    Cheng, K. H., Chang, S. M., Lo, Y. L. & Jiang, S. Y., 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits. p. 72-75 4 p. (Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    6 引文 斯高帕斯（Scopus）

  • A CMOS VCO for IV, 1GHz PLL applications

    Cheng, K. H., Lai, C. W. & Lo, Y. L., 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits. p. 150-153 4 p. (Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    15 引文 斯高帕斯（Scopus）

  • A phase-locked pulseWidth control loop with programmable duty cycle

    Cheng, K. H., Su, C. W., Wu, C. L. & Lo, Y. L., 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits. p. 84-87 4 p. (Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    8 引文 斯高帕斯（Scopus）
  • 2003

    A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation

    Cheng, K. H., Lo, Y. L., Yu, W. F. & Hung, S. Y., 2003, Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003. Ismail, Y. & Badawy, W. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 90-93 4 p. 1213012. (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）

  • A robust handshake for asynchronous system

    Cheng, K. H., Chang, W. C. & Tu, C. M., 2003, Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003. Ismail, Y. & Badawy, W. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 16-19 4 p. 1212998. (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • HIGH ACCURACY CURRENT MIRROR WITH LOW SETTLING TIME

    Cheng, K. H., Chen, T. S. & Kuo, C. W., 2003, Midwest Symposium on Circuits and Systems. Hamdy, N. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 189-192 4 p. (Midwest Symposium on Circuits and Systems; 卷 1).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）
  • 2002

    A low power, wide operating frequency and high noise immunity half-digital phased-locked loop

    Cheng, K. H. & Yang, W. B., 2002, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 263-266 4 p. 1031582. (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）

  • Influences of minimum cut plane properties on the mincut circuit partitioning problems

    Cheng, K. H. & Cheng, S. W., 2002, ICECS 2002 - 9th IEEE International Conference on Electronics, Circuits and Systems. p. 375-379 5 p. 1045412. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 1).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization

    Cheng, K. H. & Cheng, S. W., 2002, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., p. 155-159 5 p. 994909. (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）
  • 2001

    A 1.2V 500MHz 32-bit carry-lookahead adder

    Cheng, K. H., Lee, W. S. & Huang, Y. C., 2001, ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. p. 765-768 4 p. 957587. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 2).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    7 引文 斯高帕斯（Scopus）

  • Accurate current mirror with high output impedance

    Cheng, K. H., Chen, C. C. & Chung, C. F., 2001, ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. p. 565-568 4 p. 957539. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 2).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    27 引文 斯高帕斯（Scopus）

  • A CMOS low power voltage controlled oscillator with split-path controller

    Cheng, K. H., Tzou, L. J., Yang, W. B. & Sheu, S. S., 2001, ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. p. 421-424 4 p. 957769. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 1).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）

  • A difference detector PFD for low jitter PLL

    Cheng, K. H., Yao, T. H., Jiang, S. Y. & Yang, W. B., 2001, ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. p. 43-46 4 p. 957660. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 1).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    35 引文 斯高帕斯（Scopus）

  • A low-power high driving ability voltage control oscillator used in PLL

    Cheng, K. H., Yang, W. B. & Chung, C. F., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. p. 614-617 4 p. 922312. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; 卷 4).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • A new logic synthesis and optimization procedure

    Cheng, H. H. & Hsieh, V. C., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. p. 182-185 4 p. 922202. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; 卷 4).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning

    Cheng, K. H. & Cheng, S. W., 2001, ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. p. 889-893 5 p. 957616. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 2).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • ENISLE: An intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning

    Cheng, S. W. & Cheng, K. H., 2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. IEEE Computer Society, p. 167-170 4 p. 922011. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; 卷 5).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）
  • 1999

    High efficient 3-input XOR for low-voltage low-power high-speed applications

    Cheng, K. H. & Hsieh, V. C., 1999, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., p. 166-169 4 p. 824054. (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    6 引文 斯高帕斯（Scopus）

  • The suggestion for CFS CMOS buffer

    Cheng, K. H. & Yang, W. B., 1999, Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., p. 799-802 4 p. 813229. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 2).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）
  • 1998

    Low voltage low power high-speed BiCMOS multiplier

    Cheng, K. H., Yeha, Y. K. & Lian, F. S., 1998, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Institute of Electrical and Electronics Engineers Inc., p. 49-50 2 p. 814820. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; 卷 2).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）
  • 1992

    High-speed four-phase CMOS logic for complex high-speed VLSI

    Wu, C. Y., Cheng, K. H. & Wang, J. S., 1992, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., p. 1288-1291 4 p. 230269. (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 3).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審