國興 鄭 的照片

查看斯高帕斯 (Scopus) 概要

鄭 國興

教授

按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1991 …2023

每年研究成果

篩選
會議論文篇章

搜尋結果

  • 2023

    A 150mA 20ns Settling Time Low Dropout Regulator

    Huang, H. Y., Tsao, Y. M., Daroy, A. N. M. & Cheng, K. H., 2023, ICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems: Technosapiens for Saving Humanity. Institute of Electrical and Electronics Engineers Inc., (ICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems: Technosapiens for Saving Humanity).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • A Low Power 16 Gbps CTLE and Quarter-Rate DFE with Single Adaptive System

    Cheng, K. H., Chang, C. Y., Huang, H. Y. & Shih, Y. T., 2023, ICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems: Technosapiens for Saving Humanity. Institute of Electrical and Electronics Engineers Inc., (ICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems: Technosapiens for Saving Humanity).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）
  • 2019

    A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System

    Tsai, T. H., Chi, P. T. & Cheng, K. H., 4月 2019, Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Institute of Electrical and Electronics Engineers Inc., 8724656. (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）
  • 2018

    A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application

    Tsai, C. W., Chiu, Y. T., Tu, Y. H. & Cheng, K. H., 26 4月 2018, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8350995. (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 2018-May).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    8 引文 斯高帕斯（Scopus）
  • 2017

    A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering

    Tu, Y. H., Yao, K. W., Huang, M. H., Lin, Y. Y., Chi, H. Y., Cheng, P. M., Tsai, P. Y., Shiue, M. T., Liu, C. N., Cheng, K. H. & Fu, J. S., 5 6月 2017, 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 7939668. (2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）
  • 2016

    A chaotically injected timing technique for ring-based oscillators

    Tu, Y. H., Cheng, K. H., Wang, W. R., Liu, J. C. & Huang, H. Y., 31 5月 2016, Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016. Institute of Electrical and Electronics Engineers Inc., 7482467. (Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Gm-C filter with automatic calibration scheme

    Huang, H. Y., Chen, K. Y., Xie, J. H., Lee, M. T., Hong, H. C. & Cheng, K. H., 31 5月 2016, Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016. Institute of Electrical and Electronics Engineers Inc., 7482471. (Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）

  • Low-voltage indoor energy harvesting using photovoltaic cell

    Huang, H. Y., Yen, S. Z., Chen, J. H., Hong, H. C. & Cheng, K. H., 31 5月 2016, Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016. Institute of Electrical and Electronics Engineers Inc., 7482472. (Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    9 引文 斯高帕斯（Scopus）
  • 2015

    A Synchronous Mirror Delay with Duty-Cycle Tunable Technology

    Tu, Y. H., Cheng, K. H., Lin, Y. A. & Huang, H. Y., 13 8月 2015, Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015. Vierhaus, H. T., Stamenkovic, Z., Pleskacz, W. & Raik, J. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 79-82 4 p. 7195672. (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing

    Huang, H. Y., Liu, J. C., Lee, P. Y., Chen, K. Y., Chen, J. S., Cheng, K. H., Huang, T. H., Luo, C. H. & Chiou, J. C., 13 8月 2015, Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015. Vierhaus, H. T., Stamenkovic, Z., Pleskacz, W. & Raik, J. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 125-128 4 p. 7195684. (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）
  • 2014

    A 64-MHz∼640-MHz 64-phase clock generator

    Huang, H. Y., Liu, J. C., Sun, S. J., Fu, C. H. & Cheng, K. H., 30 7月 2014, Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. Pleskacz, W., Renovell, M., Kasprowicz, D., Sekanina, L. & Bernard, S. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 51-54 4 p. 6868762. (Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • A low supply voltage synchronous mirror delay with quadrature phase output

    Tu, Y. H., Cheng, K. H., Hsu, C. H. & Huang, H. Y., 30 7月 2014, Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. Bernard, S., Pleskacz, W., Kasprowicz, D., Sekanina, L. & Renovell, M. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 163-166 4 p. 6868782. (Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）
  • 2013

    A low jitter delay-locked-loop applied for DDR4

    Tu, Y. H., Cheng, K. H., Wei, H. Y. & Huang, H. Y., 2013, Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013. IEEE Computer Society, p. 98-101 4 p. 6549796. (Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    12 引文 斯高帕斯（Scopus）

  • External capacitorless low dropout linear regulator using cascode structure

    Huang, H. Y., Chen, C. Y. & Cheng, K. H., 2013, Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013. IEEE Computer Society, p. 236-239 4 p. 6549824. (Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）

  • Indoor energy harvesting using photovoltaic cell for battery recharging

    Huang, H. Y., Mocorro, C. O., Pinaso, J. & Cheng, K. H., 2013, Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013. IEEE Computer Society, p. 224-227 4 p. 6549821. (Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    11 引文 斯高帕斯（Scopus）
  • 2012

    Auto-calibration techniques in built-in jitter measurement circuit

    Cheng, C. P., Liu, J. C. & Cheng, K. H., 2012, Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012. p. 248-249 2 p. 6219066. (Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • 2011

    A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation

    Hung, C. L., Cheng, K. H., Lin, Y. C., Jiang, B. Q., Fan, C. H. & Chang, C. Y., 2011, ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. p. 447-450 4 p. 6045003. (European Solid-State Circuits Conference).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • A 3 GHz spread-spectrum clock generator with a self-calibration technique

    Chang, C. Y., Hung, C. L., Lin, Y. C. & Cheng, K. H., 2011, 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011. p. 177-180 4 p. 5981284. (2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

    Sheu, S. S., Chang, M. F., Lin, K. F., Wu, C. W., Chen, Y. S., Chiu, P. F., Kuo, C. C., Yang, Y. S., Chiang, P. C., Lin, W. P., Lin, C. H., Lee, H. Y., Gu, P. Y., Wang, S. M., Chen, F. T., Su, K. L., Lien, C. H., Cheng, K. H., Wu, H. T. & Ku, T. K. 及其他2, Kao, M. J. & Tsai, M. J., 2011, 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc., p. 200-202 3 p. 5746281. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    236 引文 斯高帕斯（Scopus）

  • All digital phase-locked loop using active inductor oscillator and novel locking algorithm

    Huang, T. C., Huang, H. Y., Liu, J. C., Cheng, K. H. & Luo, C. H., 2011, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011. p. 486-489 4 p. 5937608. (Proceedings - IEEE International Symposium on Circuits and Systems).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • A phase error calibration DLL with edge combiner for wide-range operation

    Huang, P. C., Shih, C. J., Tsai, Y. C. & Cheng, K. H., 2011, 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011. p. 1-4 4 p. 5981204. (2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    6 引文 斯高帕斯（Scopus）

  • Measurement error analysis and calibration techniques for built-in jitter measurement circuit

    Cheng, K. H., Chang, C. Y., Liu, J. C. & Cheng, C. P., 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 158-161 4 p. 5783600. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）
  • 2010

    A 3 GHz DLL-based clock generator with stuck locking protection

    Tu, Y. H., Chang, H. H., Hung, C. L. & Cheng, K. H., 2010, 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings. p. 106-109 4 p. 5724465. (2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • A CMOS adaptive equalizer using low-voltage zero generators technique

    Tsai, Y. C., Cheng, K. H., Wu, Y. H. & Lin, Y. F., 2010, ESSCIRC 2010 - 36th European Solid State Circuits Conference. p. 546-549 4 p. 5619764. (ESSCIRC 2010 - 36th European Solid State Circuits Conference).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • A high-speed current mode sense amplifier for Spin-Torque Transfer Magnetic Random Access Memory

    Cheng, C. T., Tsai, Y. C. & Cheng, K. H., 2010, 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010. p. 181-184 4 p. 5548588. (Midwest Symposium on Circuits and Systems).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    17 引文 斯高帕斯（Scopus）

  • A loading effect insensitive and high precision clock synchronization circuit

    Hong, K. W., Cheng, K. H., Chen, C. H., Liu, J. C. & Chen, C. C., 2010, ESSCIRC 2010 - 36th European Solid State Circuits Conference. p. 514-517 4 p. 5619756. (ESSCIRC 2010 - 36th European Solid State Circuits Conference).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）

  • A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

    Cheng, K. H., Hu, C. C., Liu, J. C. & Huang, H. Y., 2010, Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. p. 285-288 4 p. 5491766. (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    8 引文 斯高帕斯（Scopus）
  • 2009

    0.5V 160-MHz 260uW all digital phase-locked loop

    Liu, J. C., Huang, H. Y., Yang, W. B. & Cheng, K. H., 2009, Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009. p. 186-189 4 p. 5012125. (Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）

  • A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme

    Sheu, S. S., Chiang, P. C., Lin, W. P., Lee, H. Y., Chen, P. S., Chen, Y. S., Wu, T. Y., Chen, F. T., Su, K. L., Kao, M. J., Cheng, K. H. & Tsai, M. J., 2009, 2009 Symposium on VLSI Circuits. p. 82-83 2 p. 5205283. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    111 引文 斯高帕斯（Scopus）

  • A micro-network on chip with 10-Gb/s transmission link

    Liu, W. C., Lin, C. H., Jou, S. J., Lu, H. W., Su, C. C., Hong, K. W., Cheng, K. H., Yang, S. W. & Sheu, M. H., 2009, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 277-280 4 p. 5357256. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Designing ultra-low voltage PLL using a bulk-driven technique

    Chao, T. S., Lo, Y. L., Yang, W. B. & Cheng, K. H., 2009, ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference. p. 388-391 4 p. 5325983. (ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    14 引文 斯高帕斯（Scopus）
  • 2008

    A compact and low-power SRAM with improved read static noise margin

    Gong, C. S. A., Hong, C. T., Yao, K. W., Shiue, M. T. & Cheng, K. H., 2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. p. 546-549 4 p. 4674911. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • A high-accuracy and high-efficiency on-chip current sensing for current-mode control CMOS DC-DC buck converter

    Cheng, K. H., Su, C. W. & Ko, H. H., 2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. p. 458-461 4 p. 4674889. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    35 引文 斯高帕斯（Scopus）

  • A low jitter self-calibration PLL for 10Gbps SoC transmission links application

    Cheng, K. H., Tsai, Y. C., Hong, K. W. & Wu, Y. H., 2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. p. 786-789 4 p. 4674971. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）

  • Al-V 10-bit 2GSample/s D/A converter based on precision current reference in 90-nm CMOS

    Cheng, K. H., Wang, H. H. & Huang, D. J., 2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. p. 340-343 4 p. 4674860. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）

  • A wide-range DLL-based clock generator with phase error calibration

    Cheng, K. H., Su, C. W., Wu, M. J. & Chang, Y. L., 2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. p. 798-801 4 p. 4674974. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    9 引文 斯高帕斯（Scopus）
  • 2007

    A 100 MHz-1 GHz adaptive bandwidth PLL using TDC technique

    Cheng, K. H., Lo, Y. L., Lai, C. W. & Yang, W. B., 2007, ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. p. 1163-1166 4 p. 4511202. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery

    Cheng, K. H., Chen, C. A., Yang, W. B. & Cho, F. H., 2007, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 4239428. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • All-digital PLL using pulse-based DCO

    Huang, H. Y., Liu, J. C. & Cheng, K. H., 2007, ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. p. 1268-1271 4 p. 4511228. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）

  • A phase interpolator for sub-IV and high frequency for clock and data recovery

    Cheng, K. H., Tseng, P. K. & Lo, Y. L., 2007, ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. p. 363-366 4 p. 4511005. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）
  • 2006

    A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process

    Cheng, K. H., Chang, K. F., Lo, Y. L., Lai, C. W. & Tseng, Y. K., 2006, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. p. 3205-3208 4 p. 1693307. (Proceedings - IEEE International Symposium on Circuits and Systems).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）

  • A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs

    Cheng, K. H. & Lo, Y. L., 2006, Proceedings - Design, Automation and Test in Europe, DATE'06. 1657135. (Proceedings -Design, Automation and Test in Europe, DATE; 卷 2).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）

  • A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

    Cheng, K. H., Su, C. W., Chang, K. F., Hung, C. L. & Yang, W. B., 2006, ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. p. 178-181 4 p. 4099733. (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）

  • A variable duty cycle with high-resolution synchronous mirror delay

    Hong, K. W., Lee, C. H., Cheng, K. H., Wu, C. L. & Yang, W. B., 2006, ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems. p. 569-572 4 p. 4263430. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Design of self-sampling based ASK demodulator for implantable microsystem

    Gong, C. S. A., Wu, C. L., Ho, S. Y., Chen, T. Y., Huang, J. C., Su, C. W., Su, C. H., Chang, Y., Cheng, K. H., Lo, Y. L. & Shiue, M. T., 2006, ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems. p. 33-36 4 p. 4263297. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    8 引文 斯高帕斯（Scopus）

  • Self-sampled vernier delay line for built-in clock jitter measurement

    Cheng, K. H., Huang, C. W. & Jiang, S. Y., 2006, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. p. 1591-1594 4 p. 1692904. (Proceedings - IEEE International Symposium on Circuits and Systems).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）
  • 2005

    A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs

    Cheng, K. H. & Lo, Y. L., 2005, Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference. p. 189-192 4 p. 1541591. (Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）

  • High accuracy jitter measurement using cyclic pulse width modulation structure

    Cheng, K. H. & Jiang, S. Y., 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). p. 24-27 4 p. 1500010. (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); 卷 2005).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle

    Yang, W. B., Kuo, S. C., Chu, Y. H. & Cheng, K. H., 2005, Proceedings of the 2005 European Conference on Circuit Theory and Design. p. 193-196 4 p. 1523093. (Proceedings of the 2005 European Conference on Circuit Theory and Design; 卷 3).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）
  • 2004

    64-Bit hybrid dual-threshold voltage power-aware conditional carry adder design

    Cheng, K. H., Cheng, S. W. & Huang, C. W., 2004, Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004. Badawy, W. & Ismail, Y. (編輯). p. 65-68 4 p. (Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）