跳至主導覽
跳至搜尋
跳過主要內容
國立中央大學 首頁
說明與常見問題
English
中文
首頁
人才檔案
研究單位
研究計畫
研究成果
資料集
榮譽/獲獎
學術活動
新聞/媒體
影響
按專業知識、姓名或所屬機構搜尋
查看斯高帕斯 (Scopus) 概要
鄭 國興
教授
電機工程學系
電子郵件
cheng
ee.ncu.edu
tw
網站
http://pdc.adm.ncu.edu.tw/introduce/introduce5.htm
h-index
1491
引文
18
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1991 …
2023
每年研究成果
概覽
指紋
網路
研究計畫
(7)
研究成果
(154)
類似的個人檔案
(6)
指紋
查看啟用 Kuo-Hsing Cheng 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Low Power
75%
Supply Voltage
63%
Phase-locked Loop
58%
CMOS Process
57%
Low Voltage
52%
Fast Lock
42%
Power Consumption
41%
Voltage-controlled Oscillator
34%
Clock Generator
34%
Power Dissipation
31%
All-digital
27%
All-digital Phase-locked Loop (ADPLL)
27%
Delay-locked Loop
26%
Timing Resolution
25%
Peak-to-peak Jitter
24%
CMOS Technology
24%
Wide Operation Range
24%
Low Jitter
24%
Synchronous Mirror Delay
23%
Lock Time
22%
Duty Cycle
22%
Jitter
22%
Power Delay Product
21%
Current Sensing
21%
Build-in Jitter Measurement
21%
Clock Frequency
20%
Split Path
19%
RMS Jitter
19%
Chip Area
18%
SPICE Model
18%
Charge Pump
18%
Complementary Pass Transistor Logic
18%
High-speed Applications
17%
On chip
17%
Multi-phase Outputs
16%
Operation Speed
16%
Time-to-digital Converter
16%
Mixed Mode
15%
90-nm CMOS Technology
15%
Low Power Consumption
15%
System-on-chip
15%
Circuit Design
15%
Measurement Results
15%
Frequency multiplier
14%
Measuring Circuit
14%
Current Mode
14%
Spread Spectrum Clock Generator
14%
64-bit
14%
Operating Frequency
14%
CMOS Buffer
14%
Engineering
Supply Voltage
100%
Phase Locked Loop
98%
Electric Power Utilization
67%
Oscillator
54%
Duty Cycle
46%
Simulation Result
45%
Energy Dissipation
38%
Locked Loop
33%
Voltage-Controlled Oscillator
31%
Phase Error
30%
Power Supply
29%
Adders
29%
Operating Frequency
27%
Range Operation
25%
Clock Cycle
25%
Logic Circuit
24%
Speed Operation
24%
Amplifier
22%
Chip Area
21%
Clock Frequency
21%
Digital Converter
19%
Speed Application
19%
System-on-Chip
18%
Circuit Design
18%
Charge Pump
17%
Nodes
17%
Frequency Multiplier
17%
Clock Signal
17%
Mixed Mode
15%
Electric Delay Lines
15%
Current Mirror
15%
High Resolution
15%
Spread Spectrum
14%
Low Power Consumption
13%
Energy Engineering
13%
Equalizers
12%
Dynamic Random Access Memory
12%
Output Phase
11%
Transceiver
11%
Frequency Operation
11%
Control Loop
10%
Output Stage
10%
Logic Function
10%
Logic Synthesis
10%
Process Variation
10%
Internal Clock
10%
Resistive
10%
Phase Detector
10%
Reference Clock
10%
Delay Circuits
9%
