進福 李 的照片

查看斯高帕斯 (Scopus) 概要

李 進福

教授, 副研發長

按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1999 …2025

每年研究成果

篩選
會議論文篇章

搜尋結果

  • 2024

    Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs

    Lin, P. Y. & Li, J. F., 2024, Proceedings - 2024 29th IEEE European Test Symposium, ETS 2024. Institute of Electrical and Electronics Engineers Inc., (Proceedings of the European Test Workshop).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • 2023

    An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs

    Chen, Y. G., Huang, P. Y. & Li, J. F., 16 1月 2023, ASP-DAC 2023 - 28th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 13-18 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

    Wu, M. S., Chua, Y. L., Li, J. F., Chuan, Y. T. & Huang, S. H., 2023, Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023. Institute of Electrical and Electronics Engineers Inc., (Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Hardware Trojans of Computing-In-Memories: Issues and Methods

    Huang, S. H., Cheng, W. C. & Li, J. F., 2023, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Cassano, L., Psarakis, M., Traiola, M. & Bosio, A. (編輯). Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability

    Li, J. F., 2023, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Cassano, L., Psarakis, M., Traiola, M. & Bosio, A. (編輯). Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • 2022

    Design and Dataflow for Multibit SRAM-Based MAC Operations

    Cheng, C. H., Huang, S. H. & Li, J. F., 2022, Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., p. 159-160 2 p. (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Design and Test of Computing-In Memories

    Li, J. F., 2022, Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., p. 157-158 2 p. (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs

    Pan, Z. W. & Li, J. F., 2022, Proceedings - 2022 IEEE International Test Conference, ITC 2022. Institute of Electrical and Electronics Engineers Inc., p. 489-493 5 p. (Proceedings - International Test Conference; 卷 2022-September).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Fault Modeling and Testing of RRAM-based Computing-In Memories

    Yang, Y. C. & Li, J. F., 2022, Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022. Institute of Electrical and Electronics Engineers Inc., p. 7-12 6 p. (Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）

  • Testing and Reliability of Computing-In Memories: Solutions and Challenges

    Li, J. F., 2022, Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022. Institute of Electrical and Electronics Engineers Inc., p. 55-60 6 p. (Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）
  • 2021

    An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing

    Chang, W., Chen, Y. G., Huang, P. Y. & Li, J. F., 2021, 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021. Dilillo, L., Cassano, L. & Papadimitriou, A. (編輯). Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; 卷 2021-October).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）

  • Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults

    Tsai, Y. Y. & Li, J. F., 2021, Proceedings - 34th IEEE International System-on-Chip Conference, SOCC 2021. Qu, G., Xiong, J., Zhao, D., Muthukumar, V., Reza, M. F. & Sridhar, R. (編輯). IEEE Computer Society, p. 272-277 6 p. (International System on Chip Conference; 卷 2021-September).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）
  • 2020

    Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method

    Hsieh, T. F., Li, J. F., Lai, J. S., Lo, C. Y., Kwai, D. M. & Chou, Y. F., 9月 2020, Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020. Institute of Electrical and Electronics Engineers Inc., p. 41-46 6 p. 9226545. (Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • Testing of Configurable 8T SRAMs for In-Memory Computing

    Li, J. F., Tsai, T. L., Hsu, C. L. & Sun, C. T., 23 11月 2020, Proceedings - 2020 IEEE 29th Asian Test Symposium, ATS 2020. IEEE Computer Society, 9301535. (Proceedings of the Asian Test Symposium; 卷 2020-November).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    10 引文 斯高帕斯（Scopus）
  • 2019

    3D Test Wrapper Chain Optimization with I/O Cells Binding Considered

    Tang, F. H., Kao, H. Y., Huang, S. H. & Li, J. F., 10月 2019, IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019. Institute of Electrical and Electronics Engineers Inc., 9058794. (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

    Yang, W. H., Li, J. F., Hsu, C. L., Sun, C. T. & Huang, S. H., 10月 2019, IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019. Institute of Electrical and Electronics Engineers Inc., 9058898. (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Configurable 8T SRAM for Enbling in-Memory Computing

    Chen, H. C., Li, J. F., Hsu, C. L. & Sun, C. T., 4月 2019, 2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019. Institute of Electrical and Electronics Engineers Inc., p. 112-116 5 p. 8726871. (2019 2nd International Conference on Communication Engineering and Technology, ICCET 2019).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    12 引文 斯高帕斯（Scopus）

  • Testing of in-memory-computing 8T SRAMs

    Tsai, T. L., Li, J. F., Hsu, C. L. & Sun, C. T., 10月 2019, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019. Institute of Electrical and Electronics Engineers Inc., 8875487. (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    23 引文 斯高帕斯（Scopus）

  • Testing stuck-open faults of priority address encoder in content addressable memories

    Tsai, T. L., Li, J. F., Hsu, C. L. & Su, C. T., 21 1月 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 382-387 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）
  • 2018

    A channel-sharable built-in self-test scheme for multi-channel DRAMs

    Wu, K. T., Li, J. F., Lo, C. Y., Lai, J. S., Kwai, D. M. & Chou, Y. F., 20 2月 2018, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 245-250 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 2018-January).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Diagnosis of Resistive Nonvolatile-8T SRAMs

    Li, Y. T., Li, J. F., Hsu, C. L. & Sun, C. T., 2 7月 2018, Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., p. 23-24 2 p. 8649953. (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Modeling and testing comparison faults of memristive ternary content addressable memories

    Deng, L. W., Li, J. F. & Chen, Y. X., 29 6月 2018, Proceedings - 2018 23rd IEEE European Test Symposium, ETS 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-6 6 p. (Proceedings of the European Test Workshop; 卷 2018-May).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）
  • 2017

    A built-in self-Test scheme for classifying refresh periods of DRAMs

    Chang, C. M., Chen, Y. X. & Li, J. F., 3 7月 2017, Proceedings - 2017 22nd IEEE European Test Symposium, ETS 2017. Institute of Electrical and Electronics Engineers Inc., 7968245. (Proceedings of the European Test Workshop).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs

    Hsieh, T. F., Li, J. F., Wu, K. T., Lai, J. S., Lo, C. Y., Kwai, D. M. & Chou, Y. F., 3 11月 2017, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 107-111 5 p. 8097122. (ITC-Asia 2017 - International Test Conference in Asia).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）
  • 2016

    A built-in method for measuring the delay of TSVs in 3D ICs

    Wu, H. Y., Chen, Y. X. & Li, J. F., 22 7月 2016, Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016. Institute of Electrical and Electronics Engineers Inc., 7519293. (Proceedings of the European Test Workshop; 卷 2016-July).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

    Hou, C. S., Chen, Y. X., Li, J. F., Lo, C. Y., Kwai, D. M. & Chou, Y. F., 2 7月 2016, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805832. (Proceedings - International Test Conference; 卷 0).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    14 引文 斯高帕斯（Scopus）

  • A Test Method for Finding Boundary Currents of 1T1R Memristor Memories

    Lin, T. Y., Chen, Y. X., Li, J. F., Lo, C. Y., Kwai, D. M. & Chou, Y. F., 22 12月 2016, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 281-286 6 p. 7796127. (Proceedings of the Asian Test Symposium).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）

  • Fault modeling and testing of resistive nonvolatile-8T SRAMs

    Li, Y. T., Chen, Y. X. & Li, J. F., 23 5月 2016, Proceedings - 2016 IEEE 34th VLSI Test Symposium, VTS 2016. IEEE Computer Society, 7477303. (Proceedings of the IEEE VLSI Test Symposium; 卷 2016-May).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）
  • 2015

    A hybrid built-in self-test scheme for DRAMs

    Yang, C. C., Li, J. F., Yu, Y. C., Wu, K. T., Lo, C. Y., Chen, C. H., Lai, J. S., Kwai, D. M. & Chou, Y. F., 28 5月 2015, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 7114502. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    6 引文 斯高帕斯（Scopus）

  • Fault modeling and testing of 1T1R memristor memories

    Chen, Y. X. & Li, J. F., 1 6月 2015, Proceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015. IEEE Computer Society, 7116247. (Proceedings of the IEEE VLSI Test Symposium; 卷 2015-January).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    61 引文 斯高帕斯（Scopus）

  • Testing Inter-Word Coupling Faults of Wide I/O DRAMs

    Chou, C. W., Chen, Y. X. & Li, J. F., 28 2月 2015, Proceedings - 2015 24th IEEE Asian Test Symposium, ATS 2015. IEEE Computer Society, p. 67-72 6 p. 7422237. (Proceedings of the Asian Test Symposium; 卷 2016-February).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）
  • 2014

    BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs

    Yu, Y. C., Yang, C. C., Li, J. F., Lo, C. Y., Chen, C. H., Lai, J. S., Kwai, D. M., Chou, Y. F. & Wu, C. W., 7 12月 2014, Proceedings - 23rd Asian Test Symposium, ATS 2014. IEEE Computer Society, p. 1-6 6 p. 06979068. (Proceedings of the Asian Test Symposium).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Intra-channel reconfigurable interface for TSV and micro bump fault tolerance in 3-d RAMs

    Wu, K. T., Li, J. F., Yu, Y. C., Hou, C. S., Yang, C. C., Kwai, D. M., Chou, Y. F. & Lo, C. Y., 7 12月 2014, Proceedings - 23rd Asian Test Symposium, ATS 2014. IEEE Computer Society, p. 143-148 6 p. 06979091. (Proceedings of the Asian Test Symposium).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Testing of non-volatile logic-based system chips

    Chen, Y. X. & Li, J. F., 7 12月 2014, Proceedings - 23rd Asian Test Symposium, ATS 2014. IEEE Computer Society, p. 224-229 6 p. 06979104. (Proceedings of the Asian Test Symposium).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • 2013

    A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

    Yu, Y. C., Hou, C. S., Chang, L. J., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548927. (Proceedings of the IEEE VLSI Test Symposium).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    6 引文 斯高帕斯（Scopus）

  • Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs

    Hou, C. S. & Li, J. F., 2013, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548940. (Proceedings of the IEEE VLSI Test Symposium).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）

  • An FPGA-based test platform for analyzing data retention time distribution of DRAMs

    Hou, C. S., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533853. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    14 引文 斯高帕斯（Scopus）
  • 2012

    A built-in self-test scheme for 3D RAMs

    Yu, Y. C., Chou, C. W., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2012, ITC 2012 - International Test Conference 2012, Proceedings. 6401579. (Proceedings - International Test Conference).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）

  • Area and reliability efficient ECC scheme for 3D RAMs

    Chang, L. J., Huang, Y. J. & Li, J. F., 2012, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 6212645. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    7 引文 斯高帕斯（Scopus）

  • Disturbance fault testing on various NAND flash memories

    Hou, C. S. & Li, J. F., 2012, Proceedings - 2012 17th IEEE European Test Symposium, ETS 2012. 6233030. (Proceedings - 2012 17th IEEE European Test Symposium, ETS 2012).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

  • On test and repair of 3D random access memory

    Wu, C. W., Lu, S. K. & Li, J. F., 2012, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 744-749 6 p. 6165054. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    13 引文 斯高帕斯（Scopus）

  • Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

    Huang, Y. J., Li, J. F. & Chou, C. W., 2012, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 6212658. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    19 引文 斯高帕斯（Scopus）

  • Test cost optimization technique for the pre-bond test of 3D ICs

    Chen, Y. X., Huang, Y. J. & Li, J. F., 2012, Proceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012. p. 102-107 6 p. 6231087. (Proceedings of the IEEE VLSI Test Symposium).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    2 引文 斯高帕斯（Scopus）
  • 2011

    A built-in redundancy-analysis scheme for RAMs with 3D redundancy

    Chang, Y. J., Huang, Y. J. & Li, J. F., 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 264-267 4 p. 5783626. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    4 引文 斯高帕斯（Scopus）

  • A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

    Huang, Y. J., Li, J. F., Chen, J. J., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2011, Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. p. 20-25 6 p. 5783749. (Proceedings of the IEEE VLSI Test Symposium).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    70 引文 斯高帕斯（Scopus）

  • Built-in self-diagnosis and test time reduction techniques for NAND flash memories

    Chou, C. W., Hou, C. S. & Li, J. F., 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 260-263 4 p. 5783625. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    3 引文 斯高帕斯（Scopus）
  • 2010

    A low-cost and scalable test architecture for multi-core chips

    Chi, C. C., Wu, C. W. & Li, J. F., 2010, 2010 15th IEEE European Test Symposium, ETS'10. p. 30-35 6 p. 5512784. (2010 15th IEEE European Test Symposium, ETS'10).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    6 引文 斯高帕斯（Scopus）

  • A low-cost Built-in Self-Test scheme for an array of memories

    Huang, Y. J., Chou, C. W. & Li, J. F., 2010, 2010 15th IEEE European Test Symposium, ETS'10. p. 75-80 6 p. 5512779. (2010 15th IEEE European Test Symposium, ETS'10).

    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）

  • A test integration methodology for 3D integrated circuits

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    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    29 引文 斯高帕斯（Scopus）

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    研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

    5 引文 斯高帕斯（Scopus）