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查看斯高帕斯 (Scopus) 概要
李 進福
教授, 副研發長
電機工程學系
電子郵件
jfli
ee.ncu.edu
tw
網站
http://www.ee.ncu.edu.tw/~jfli/
h-index
1688
引文
22
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1999 …
2025
每年研究成果
概覽
指紋
網路
研究計畫
(18)
研究成果
(148)
類似的個人檔案
(6)
指紋
查看啟用 Jin-Fu Li 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
3D IC
18%
8T SRAM
19%
Analysis Scheme
26%
Area Cost
42%
Area Overhead
27%
Asymmetric Cell
21%
Binary Content-addressable Memory
18%
Built-in Redundancy Analysis
44%
Built-in Self-Diagnosis
19%
Built-in Self-repair
99%
Built-in-self-test (BiST)
89%
Comparison Faults
53%
Compression Techniques
16%
Content-addressable Memory
47%
Coupling Faults
20%
Diagnosis Scheme
20%
Diagnostic Algorithm
18%
Dynamic Random Access Memory
25%
Embedded Memory
43%
Encoder
18%
Error Correction Codes
20%
Fast Fourier Transform
19%
Fault Model
18%
Fault Test
19%
In-memory Computing
28%
Local Bitmap
16%
March Test
22%
Memory Cell
16%
Memristor
17%
NAND Flash Memory
19%
Random Access Memory
100%
Reconfigurable
17%
Redundancy
56%
Redundancy Analysis Algorithm
30%
Repair Method
21%
Repair Rate
28%
Repair Scheme
70%
Static Random Access Memory
25%
System-on-chip
52%
System-on-chip Design
20%
Ternary Content Addressable Memory
62%
Test Circuit
21%
Testing Algorithm
43%
Testing Method
19%
Three-dimensional (3D)
38%
Three-Dimensional ICs
34%
Through Silicon via
36%
Transform Network
17%
Write Operation
31%
Yield Improvement
28%
Computer Science
Analysis of Algorithm
9%
build-in self-test
64%
Code Compression
9%
Compression Scheme
7%
Compression Technique
20%
Computer Aided Manufacturing
15%
Computer Architecture
15%
Computer Hardware
9%
Content-Addressable Memory
55%
Data Compression
7%
Data Retention
9%
Diagnosis Algorithm
15%
Dynamic Random Access Memory
10%
embedded memory
49%
Emerging Technology
8%
Erase Operation
9%
Error Correction Code
11%
Experimental Result
55%
Fast Fourier Transform
19%
Fault Diagnosis
9%
Fault Location
12%
Fault Tolerant
14%
fault-tolerance
8%
Flash Memory
12%
Hardware Overhead
12%
Input/Output
13%
Integrated Circuit
9%
Integrated Circuit Design
9%
Integration Technology
12%
Memory Array
10%
Memory Multiple
11%
Multicore
18%
Networks on Chips
7%
Process Variation
8%
Random Access Memory
97%
Reconfiguration
19%
Redundancy Analysis
77%
Redundancy Level
9%
Semiconductor Memory
10%
Static Random Access Memory
19%
System on a Chip
7%
System-on-Chip
65%
ternary content addressable memory
57%
ternary content-addressable memory
26%
Test Algorithm
49%
Test Methodology
9%
through silicon vias
30%
Time Complexity
23%
Write Operation
36%
Yield Enhancement
22%
Engineering
Adders
14%
Area Overhead
24%
Area Reduction
7%
Built-in Self Test
80%
Compression Ratio
7%
Compression Scheme
9%
Compression Technique
21%
Computer Aided Manufacturing
15%
Correction Code
6%
Crosstalk
9%
Data Diagnostics
9%
Data Retention
10%
Dynamic Random Access Memory
20%
Electric Network Analysis
7%
Energy Engineering
10%
Erase Operation
14%
Error Correction
11%
Experimental Result
38%
Fast Fourier Transform
19%
Fault Diagnosis
10%
Fault Model
10%
Faulty Cell
12%
Final Yield
7%
Fits and Tolerances
8%
Flash Memory
14%
Hardware Overhead
14%
High Performance Networking
9%
Integrated Circuit
7%
Integrated Circuit Design
12%
Memory Array
7%
Nanoscale
6%
Process Variation
6%
Production Volume
8%
Random Access Memory
92%
Reconfigurability
7%
Reconfiguration
9%
Reliability Availability and Maintainability (Reliability Engineering)
94%
Repair Design
8%
Resistive
12%
Simulation Result
22%
System-on-Chip
57%
Technology Integration
15%
Test Circuit
29%
Test Data
8%
Test Group
9%
Test Method
12%
Test Technique
11%
Test Time
34%
Testability
7%
Three Dimensional Integrated Circuits
8%
