跳至主導覽
跳至搜尋
跳過主要內容
國立中央大學 首頁
說明與常見問題
English
中文
首頁
人才檔案
研究單位
研究計畫
研究成果
資料集
榮譽/獲獎
學術活動
新聞/媒體
影響
按專業知識、姓名或所屬機構搜尋
查看斯高帕斯 (Scopus) 概要
謝 易叡
副教授
電機工程學系
電子郵件
erayhsieh
cc.ncu.edu
tw
網站
http://www2.ee.ncu.edu.tw/member.html?type=2
h-index
398
引文
11
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2008
2024
每年研究成果
概覽
指紋
網路
研究計畫
(5)
研究成果
(85)
類似的個人檔案
(6)
指紋
查看啟用 E-Ray Hsieh 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Fin Field-effect Transistor (FinFET)
100%
CMOS Devices
84%
MOSFET
68%
Transistor
52%
High Performance
52%
Non-volatile Memory
48%
NMOSFET
47%
High-k Metal Gate
45%
Current Variation
40%
Drain Current
40%
PMOSFET
39%
Tri-gate
36%
SiGe
29%
Resistive Gate
26%
Tunneling
26%
Random Telegraph Noise
24%
Sneak Path
23%
CMOS Technology
22%
Tunnel FET
22%
Resistive Random Access Memory (ReRAM)
22%
Embedded Applications
21%
Measurement Techniques
21%
Random Trap Fluctuation
21%
14nm FinFET
20%
Dielectric
19%
Noise Measurement
19%
Tri-gate MOSFET
19%
Dipole
19%
Physical Unclonable Function
19%
Stress-induced
19%
Low Power
19%
Advanced CMOS
18%
Gate Current
18%
Gate Capacitance
18%
Surface Roughness
17%
Carrier Transport
17%
Temperature Effect
17%
Out-diffusion
17%
Random Dopant Fluctuation
16%
3-bits
16%
True Random number Generator
16%
Strained Silicon
16%
Injection Velocity
16%
Device Reliability
16%
Off-state Leakage Current
15%
Trigate FinFET
15%
Current Enhancement
15%
High Density
15%
HfO2
14%
N-channel
14%
Engineering
Metal-Oxide-Semiconductor Field-Effect Transistor
96%
Nodes
50%
Nonvolatile Memory
48%
Dopants
48%
Current Drain
46%
Tunnel Construction
46%
Metal Gate
38%
Resistive
36%
Dielectrics
35%
Induced Stress
26%
Internet of Things
26%
Injection Velocity
25%
Gate Dielectric
24%
Field Effect Transistor
24%
Active Power
19%
Measurement Noise
19%
Gate Capacitance
19%
Field-Effect Transistor
19%
Experimental Result
17%
Parasitic Capacitance
16%
Random Number
16%
Gate Oxide
16%
Lateral Direction
16%
Embedded Application
16%
Oxide Thickness
15%
Roughness Effect
14%
Hamming Distance
14%
Fin Height
14%
Interface Trap
13%
Transients
12%
Control Channel
12%
Design Guideline
12%
Heating Effect
12%
Flash Memory
12%
Channel Device
11%
Device Performance
11%
Channel Length
11%
Bit Error Rate
10%
Compressive Strain
10%
Active Region
9%
Moore's Law
9%
Dynamic Random Access Memory
9%
Active Fin
9%
Nitride
9%
Electric Power Utilization
9%
Reliability Availability and Maintainability (Reliability Engineering)
9%
Data Retention
9%
Current Drive
9%
Noise Margin
8%
Side Wall
8%
