跳至主導覽
跳至搜尋
跳過主要內容
國立中央大學 首頁
說明與常見問題
English
中文
首頁
人才檔案
研究單位
研究計畫
研究成果
資料集
榮譽/獲獎
學術活動
新聞/媒體
影響
按專業知識、姓名或所屬機構搜尋
查看斯高帕斯 (Scopus) 概要
許 鈞瓏
副教授
電機工程學系
網站
https://ee.ncu.edu.tw/member.html?type=1
h-index
482
引文
12
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2002
2022
每年研究成果
概覽
指紋
網路
研究成果
(64)
類似的個人檔案
(6)
指紋
查看啟用 Chun-Lung Hsu 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Static Random Access Memory
89%
Motion Estimation
88%
In-memory Computing
77%
Built-in-self-test (BiST)
75%
8T SRAM
66%
Wafer Defect Pattern
61%
Wafer Map
50%
Defect Pattern
48%
Defect Pattern Recognition
48%
Architectural Design
46%
Testing Application
46%
H.264 Encoder
44%
Encoder
44%
Area Overhead
40%
Current Mode
35%
Self-detection
33%
High Efficiency
33%
Wafer
33%
Discrete Cosine Transform
33%
Fault Aware
33%
High Performance
33%
Error Correction Codes
33%
3D IC
29%
Prediction Model
29%
Detection Method
29%
Testing Scheme
28%
Scratch Defect
27%
On-wafer Measurement
27%
Phase-locked Loop
27%
Proposed Architecture
26%
Hardware Overhead
25%
Video Coding
25%
Flash Memory
24%
Defect Type
24%
Encoding Time
23%
Error Detection
22%
Memory Array
22%
Machine Learning-based Detection
22%
Content-addressable Memory
22%
Stuck-at Faults
22%
Memory Application
22%
In Content
22%
Scratch Line
22%
Sense Amplifier
22%
Induced Defects
22%
Yield Learning
22%
Surface Electromyography (sEMG)
22%
Field Programmable Gate Arrays
22%
Intra Prediction Mode
22%
Pattern Recognition
22%
Engineering
Built-in Self Test
100%
Motion Estimation
88%
Experimental Result
78%
Random Access Memory
67%
Pattern Recognition
61%
Simulation Result
40%
Area Overhead
38%
Phase Locked Loop
37%
Good Performance
37%
Learning System
35%
Based Detection Method
33%
Error Correction
31%
Recognition Rate
29%
Error Detection
28%
Realization
27%
Correction Code
27%
Reliability Availability and Maintainability (Reliability Engineering)
27%
Computer Aided Manufacturing
26%
Field Programmable Gate Arrays
25%
Hardware Overhead
25%
Test Structure
25%
Electric Power Utilization
24%
Resistive
23%
Prediction Mode
22%
Mode Selection
22%
Current Sensor
22%
Head Orientation
22%
Induced Defect
22%
Error Tolerance
22%
Sense Amplifier
22%
Virtual Reality
22%
Resonator
22%
Flash Memory
22%
Test Time
21%
Data Retention
17%
Test Data
16%
Selection Method
16%
Edge Information
16%
Test Result
16%
Bit Rate
15%
Learning Algorithm
14%
Current Mirror
13%
Deep Learning Method
13%
Integrated Circuit
13%
Analog Circuit
13%
Network Application
13%
Charge Pump
13%
Network-on-Chip
12%
Performance Analysis
12%
Charge Pump Circuits
12%
Computer Science
Computer Architecture
55%
Static Random Access Memory
55%
Motion Estimation
55%
Error Correction Code
33%
Flash Memory
33%
Architecture Design
32%
Experimental Result
32%
Prediction Model
28%
Memory Array
28%
Error Detection
28%
Pattern Recognition
27%
Discrete Cosine Transform
24%
Networks on Chips
24%
Head Orientation
22%
Content-Addressable Memory
22%
Electromyography
22%
Virtual Reality Application
22%
Error Tolerance
22%
build-in self-test
22%
Unsupervised Learning
20%
Good Performance
19%
Hardware Architecture
17%
Hardware Overhead
16%
Power Consumption
15%
Fault detection
15%
Input/Output
14%
Field Programmable Gate Arrays
14%
ternary content addressable memory
13%
Deep Learning Method
13%
Machine Learning
12%
Learning System
12%
Computer Aided Manufacturing
12%
Test Algorithm
12%
Performance Evaluation
11%
Quiescent Supply Current
11%
Logic Block Observer
11%
Sensor Placement
11%
Semisupervised Learning
11%
Test Framework
11%
Detection Method
11%
Human Intervention
11%
Depthwise Separable Convolution
11%
Boundary Strength
11%
Parallel Architectures
11%
Data Recovery
11%
Computational Complexity
11%
video encoding
11%
de-nosing
11%
Mesh Network
11%
Inverse Quantization
11%
