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會議論文篇章

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  • 1997

    Studies of the effects of multi-stack multiquantum barrier on the properties of 1.3 μm AlGaInAs/InP quantum well lasers

    Pan, J. W., Chyi, J. I., Tu, Y. K. & Liaw, J. W., 1997, Proceedings of the IEEE 24th International Symposium on Compound Semiconductors, ISCS 1997. Melloch, M. & Reed, M. A. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 401-404 4 p. 711671. (Proceedings of the IEEE 24th International Symposium on Compound Semiconductors, ISCS 1997).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • 1996

    A fast and sensitive built-in current sensor for IDDQ testing

    Lu, C. W., Lee, C. L. & Chen, J. E., 1996, Digest of Papers - 1996 IEEE International Workshop on IDDQ Testing, IDDQ 1996. Tong, C. & Jayasuniana, A. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 56-58 3 p. 557816. (Digest of Papers - 1996 IEEE International Workshop on IDDQ Testing, IDDQ 1996).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    18 引文 斯高帕斯(Scopus)
  • Application of EKF and RLS estimators in induction motor drive

    Lin, F. J., 1996, PESC Record - IEEE Annual Power Electronics Specialists Conference. p. 713-718 6 p. (PESC Record - IEEE Annual Power Electronics Specialists Conference; 卷 1).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    6 引文 斯高帕斯(Scopus)
  • 1994

    Algebraic division for multilevel logic synthesis of multi-valued logic circuits

    Wang, H. M., Lee, C. L. & Chen, J. E., 1994, Proceedings of The International Symposium on Multiple-Valued Logic. Publ by IEEE, p. 44-51 8 p. (Proceedings of The International Symposium on Multiple-Valued Logic).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    7 引文 斯高帕斯(Scopus)
  • Complete test set for multiple-valued logic networks

    Wang, H. M., Lee, C. L. & Chen, J. E., 1994, Proceedings of The International Symposium on Multiple-Valued Logic. Publ by IEEE, p. 289-296 8 p. (Proceedings of The International Symposium on Multiple-Valued Logic).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    2 引文 斯高帕斯(Scopus)
  • Distributed fault simulation for sequential circuits by pattern partitioning

    Wu, W. C., Lee, C. L., Chen, J. E. & Lin, W. Y., 1994, Proceedings of the European Design and Test Conference. Anon (編輯). Publ by IEEE, p. 661 1 p. (Proceedings of the European Design and Test Conference).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • TRANS: A fast and memory-efficient path delay fault simulator

    Lin, M. C., Chen, J. E. & Lee, C. L., 1994, Proceedings of the European Design and Test Conference. Anon (編輯). Publ by IEEE, p. 508-512 5 p. (Proceedings of the European Design and Test Conference).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    3 引文 斯高帕斯(Scopus)
  • 1993

    An efficient trapped-charge calculation in amorphous silicon for device simulation

    Tsai, Y. T., Hong, K. D. & Yuan, Y. L., 1993, SMS 1993 Technical Digest - 1993 Symposium on Semiconductor Modeling and Simulation. Institute of Electrical and Electronics Engineers Inc., p. 75-76 2 p. 664564. (SMS 1993 Technical Digest - 1993 Symposium on Semiconductor Modeling and Simulation).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • A robust induction motor servo drive

    Liaw, C. M. & Lin, F. J., 1993, ISIE 1993 - Budapest: IEEE International Symposium on Industrial Electronics, Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 740-746 7 p. 268851. (IEEE International Symposium on Industrial Electronics).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    9 引文 斯高帕斯(Scopus)
  • A two-phase fault simulation scheme for sequential circuits

    Wu, W. C., Lee, C. L. & Chen, J. E., 1993, ATS 1993 Proceedings - 2nd Asian Test Symposium. IEEE Computer Society, p. 60-65 6 p. 398780. (Proceedings of the Asian Test Symposium).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • Fabrication/characterization of a pseudomorphic Ga0.1In0.9P/InP MESFET

    Feng, M. S., Hsin, Y. M. & Wu, C. H., 1993, III-V Electronic and Photonic Device Fabrication and Performance. Publ by Materials Research Society, p. 61-66 6 p. (Materials Research Society Symposium Proceedings; 卷 300).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • New simplified method to design a robust position controller for a DC servomotor

    Jinn-Der, W., Yau-Tarng, J. & Kuo-chin, F., 1993, Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering. Publ by IEEE, p. 607-610 4 p. (Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • Pole-assignment robustness for discrete-time systems with multiple time-delays

    Wang, R. J. & Wang, W. J., 1993, Proceedings of the IEEE Conference on Decision and Control. Publ by IEEE, p. 3831-3834 4 p. (Proceedings of the IEEE Conference on Decision and Control; 卷 4).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    6 引文 斯高帕斯(Scopus)
  • 1992

    A new robust stability criterion for interval time-delay systems

    Wang, W. J., Chiou, J. S. & Jeng, Y. S., 1992, Proceedings of the IEEE International Conference on Systems Engineering. Institute of Electrical and Electronics Engineers Inc., p. 428-431 4 p. 236996. (Proceedings of the IEEE International Conference on Systems Engineering).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • Control of indirect field-oriented induction motor drives considering the effects of dead-time and parameter variations

    Lin, F. J. & Liaw, C. M., 1992, Proceedings of the IEEE International Symposium on Industrial Electronics, ISIE 1992. Institute of Electrical and Electronics Engineers Inc., p. 658-662 5 p. 279684. (IEEE International Symposium on Industrial Electronics).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • Fault analysis on two-level (K + 1)-valued logic circuits

    Wang, H. M., Lee, C. L. & Chen, J. E., 5月 1992, Proceedings of The International Symposium on Multiple-Valued Logic. Publ by IEEE, p. 181-188 8 p. (Proceedings of The International Symposium on Multiple-Valued Logic).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • High-speed four-phase CMOS logic for complex high-speed VLSI

    Wu, C. Y., Cheng, K. H. & Wang, J. S., 1992, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., p. 1288-1291 4 p. 230269. (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 3).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • Timing-driven partial scan

    Jou, J. Y. & Cheng, K. T., 1992, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. Publ by IEEE, p. 404-407 4 p. (1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    15 引文 斯高帕斯(Scopus)
  • 1990

    A single-state-transition fault model for sequential machines

    Cheng, K. T. & Jou, J. Y., 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 226-229 4 p. (1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    22 引文 斯高帕斯(Scopus)
  • Functional test generation for finite state machines

    Cheng, K. T. & Jou, J. Y., 9月 1990, Digest of Papers - International Test Conference. Publ by IEEE, p. 162-168 7 p. (Digest of Papers - International Test Conference).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    37 引文 斯高帕斯(Scopus)
  • Simulation based verification of register-transfer level behavioral synthesis tools

    Ernst, R., Sutarwala, S., Jou, J. Y. & Tong, M., 1990, Proceedings of the European Design Automation Conference, EDAC 1990. Institute of Electrical and Electronics Engineers Inc., p. 396-400 5 p. 136680. (Proceedings of the European Design Automation Conference, EDAC 1990).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    1 引文 斯高帕斯(Scopus)
  • Single-fault fault collapsing analysis in sequential logic circuits

    Chen, J. E., Lee, C. L. & Shen, W. Z., 9月 1990, Digest of Papers - International Test Conference. Publ by IEEE, p. 809-814 6 p. (Digest of Papers - International Test Conference).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    1 引文 斯高帕斯(Scopus)
  • 1989

    TSG - A test system generator for debugging and regression test of high-level behavioral synthesis tools

    Ernst, R., Sutarwala, S. & Jou, J. Y., 1989, 20 Int Test Conf 1989 ITC. Anon (編輯). Publ by IEEE, p. 937 1 p. (20 Int Test Conf 1989 ITC).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • 1988

    BECOME: Behavior level circuit synthesis based on structure mapping.

    Wei, R. S., Rothweiler, S. & Jou, J. Y., 1988, Proceedings - Design Automation Conference. Publ by IEEE, p. 409-414 6 p. (Proceedings - Design Automation Conference).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    3 引文 斯高帕斯(Scopus)
  • SLOPE: A test pattern generator based on stop line oriented path end algorithm

    Chuang, S. J., Lee, C. L., Shen, W. Z., Jen, C. W., Chen, J. E., Jing, S. C. & Chen, M. D., 1988, Proceedings - IEEE International Symposium on Circuits and Systems. Publ by IEEE, p. 437-439 3 p. (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 1).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    2 引文 斯高帕斯(Scopus)
  • Testable PLA design with low overhead and ease of test generation

    Jou, J. Y., 1988, 1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc. Publ by IEEE, p. 450-453 4 p. (1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

  • 1985

    FAULT-TOLERANT FFT NETWORKS.

    Jou, J. Y. & Abraham, J. A., 1985, Digest of Papers - FTCS (Fault-Tolerant Computing Symposium). IEEE, p. 338-343 6 p. (Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    17 引文 斯高帕斯(Scopus)
  • 1984

    BUILT-IN TEST FOR VLSI FINITE-STATE MACHINES.

    Hua, K. A., Jou, J. Y. & Abraham, J. A., 1984, Digest of Papers - FTCS (Fault-Tolerant Computing Symposium). IEEE, p. 292-297 6 p. (Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)).

    研究成果: 書貢獻/報告類型會議論文篇章同行評審

    27 引文 斯高帕斯(Scopus)