Yield-enhancement techniques for 3D random access memories

Che Wei Chou, Yu Jen Huang, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

33 Scopus citations

Abstract

Three-dimensional (3D) integration technology using through silicon via (TSV) is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for using the 3D integration technology. Introducing redundancies into a large-capacity RAM in design phase is essential for yield improvement. In this paper, we present yield-enhancement techniques for 3D RAMs. In addition to typical redundancy schemes are used to improve the yield of 3D RAMs, an inter-die redundancy scheme is proposed. Also, a stacking flow is proposed to further improve the final yield of 3D RAMs with the proposed inter-die redundancy scheme.

Original languageEnglish
Title of host publicationProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages104-107
Number of pages4
DOIs
StatePublished - 2010
Event2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan
Duration: 26 Apr 201029 Apr 2010

Publication series

NameProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Conference

Conference2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Country/TerritoryTaiwan
CityHsin Chu
Period26/04/1029/04/10

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