Yield-award placement optimization for Switched-Capacitor analog integrated circuits

Chien Chih Huang, Jwu E. Chen, Pei Wen Luo, Chin Long Wey

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Paralleling square unit capacitors have been commonly used for Switched-Capacitor circuits to achieve higher accurate capacitor ratio. However, the capacitor ratio may be shifted due to the wire interconnection of these unit capacitors. The small capacitor ratio shift may cause a significant yield drop. The ratio shift can be reduced by using extra circuitry to achieve parasitic insensitive design. This study presents a simple a layout modification to alleviate the ratio shift, thus enhancing yield, without requiring extra circuitry.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2011
Pages170-173
Number of pages4
DOIs
StatePublished - 2011
Event24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan
Duration: 26 Sep 201128 Sep 2011

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference24th IEEE International System on Chip Conference, SOCC 2011
Country/TerritoryTaiwan
CityTaipei
Period26/09/1128/09/11

Keywords

  • Yield-Award
  • layout generator
  • physical realization
  • random variation
  • spatial correlation

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