Wide-range synchronous mirror delay with arbitrary input duty cycle

K. H. Cheng, C. W. Su, S. W. Lu

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

A wide-range synchronous mirror delay (SMD) with arbitrary input duty cycle is presented. The proposed SMD utilises the time-to-digital converter for a frequency-range selector and a multiband delay monitor circuit to achieve a wide range of operating frequencies. The simulation results show that the operating frequency is from 200 MHz to 1 GHz and the static phase error is 6.7 ps. The locking time is less than eight clock cycles: two cycles with coarse tune and six cycles with fine tune.

Original languageEnglish
Pages (from-to)665-667
Number of pages3
JournalElectronics Letters
Volume44
Issue number11
DOIs
StatePublished - 2008

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