Wafer map defect classification with depthwise separable convolutions

Tsung Han Tsai, Yu Chen Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

In the IC design process, the test process is the main factor of production cost. Existing tests rely on additional analysis of testing result data by the engineer to determine the status of the process. Thus it could take an additional amount of time and cannot make adjustments of the process immediately. Wafer map defect recognition is an import part of semiconductor. There is lots of information in wafer maps which can quickly help engineers to identify what failure type it is. The location of the error point is graphical represented and the relationship of these points contains the feature of this map. In this paper, we proposed a classifier with reduced-weight architecture based on depthwise separable convolutions. The entire work is verified by using the real-world wafer map dataset (WM-811K). The accuracy is 96.63% in test set.

Original languageEnglish
Title of host publication2020 IEEE International Conference on Consumer Electronics, ICCE 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728151861
DOIs
StatePublished - Jan 2020
Event2020 IEEE International Conference on Consumer Electronics, ICCE 2020 - Las Vegas, United States
Duration: 4 Jan 20206 Jan 2020

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
Volume2020-January
ISSN (Print)0747-668X

Conference

Conference2020 IEEE International Conference on Consumer Electronics, ICCE 2020
Country/TerritoryUnited States
CityLas Vegas
Period4/01/206/01/20

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