Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis

Ken Chau Cheung Cheng, Katherine Shu-Min Li, Andrew Yi Ann Huang, Ji Wei Li, Leon Li Yang Chen, Nova Cheng-Yen Tsai, Sying Jyan Wang, Chen Shiun Lee, Leon Chou, Peter Yi Yu Liao, Hsing Chung Liang, Jwu E. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

Original languageEnglish
Title of host publicationProceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
EditorsGiorgio Di Natale, Cristiana Bolchini, Elena-Ioana Vatajelu
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1710-1711
Number of pages2
ISBN (Electronic)9783981926347
DOIs
StatePublished - Mar 2020
Event2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 - Grenoble, France
Duration: 9 Mar 202013 Mar 2020

Publication series

NameProceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

Conference

Conference2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
Country/TerritoryFrance
CityGrenoble
Period9/03/2013/03/20

Keywords

  • test path recognition
  • test yield
  • test-induced defects
  • wafer defect map
  • wafer test

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