VLSI Implementation of Lossless ECG Compression Algorithm for Low Power Devices

Tsung Han Tsai, Muhammad Awais Hussain

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

This brief presents a VLSI implementation of an efficient lossless compression scheme for electrocardiogram (ECG) data encoding to save storage space and reduce transmission time. As compression algorithm is able to save storage space and reduce transmission time, this opportunity has been seized by implementing memory-less design while working at a high clock speed in VLSI. ECG compression algorithm comprises two parts: an adaptive linear prediction technique and content-adaptive Golomb Rice code. An efficient and low power VLSI implementation of compression algorithm has been presented. To improve the performance, the proposed VLSI design uses bit shifting operations as a replacement for the different arithmetic operations. VLSI implementation has been applied to the MIT-BIH arrhythmia database which is able to achieve a lossless bit compression rate of 2.77. Moreover, VLSI architecture contains 3.1 K gate count and core of the chip consumes 27.2 nW of power while working at 1 KHz frequency. The core area is 0.05 mm2 in 90 nm CMOS process.

Original languageEnglish
Article number9025261
Pages (from-to)3317-3321
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume67
Issue number12
DOIs
StatePublished - Dec 2020

Keywords

  • ECG compression
  • Golomb rice coding
  • VLSI
  • adaptive linear prediction
  • low power design

Fingerprint

Dive into the research topics of 'VLSI Implementation of Lossless ECG Compression Algorithm for Low Power Devices'. Together they form a unique fingerprint.

Cite this