VLSI implementation of 3-D sound generator

An Nan Suen; Jhing Fa Wang; Jia Ching Wang

VLSI implementation of 3-D sound generator

An Nan Suen, Jhing Fa Wang, Jia Ching Wang

Research output: Contribution to journal › Conference article › peer-review

Abstract

A high performance VLSI architecture is proposed for the 3D sound generation chip. A single 3D sound chip design reduces the cost and size of many audio systems. The proposed 3D sound VLSI architecture has the following merits: excellent accuracy results due to the accuracy studies for the finite word length; high speed operations owing to the high performance concurrent processing structure; and real-time response for 44.1 KHz sampling data.

Original language	English
Pages (from-to)	296-297
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
State	Published - 1997
Event	Proceedings of the 1997 16th International Conference on Consumer Electronics, ICCE - Rosemont, IL, USA Duration: 11 Jun 1997 → 13 Jun 1997

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title = "VLSI implementation of 3-D sound generator",

abstract = "A high performance VLSI architecture is proposed for the 3D sound generation chip. A single 3D sound chip design reduces the cost and size of many audio systems. The proposed 3D sound VLSI architecture has the following merits: excellent accuracy results due to the accuracy studies for the finite word length; high speed operations owing to the high performance concurrent processing structure; and real-time response for 44.1 KHz sampling data.",

author = "Suen, {An Nan} and Wang, {Jhing Fa} and Wang, {Jia Ching}",

year = "1997",

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pages = "296--297",

journal = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

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note = "Proceedings of the 1997 16th International Conference on Consumer Electronics, ICCE ; Conference date: 11-06-1997 Through 13-06-1997",

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T1 - VLSI implementation of 3-D sound generator

AU - Suen, An Nan

AU - Wang, Jhing Fa

AU - Wang, Jia Ching

PY - 1997

Y1 - 1997

N2 - A high performance VLSI architecture is proposed for the 3D sound generation chip. A single 3D sound chip design reduces the cost and size of many audio systems. The proposed 3D sound VLSI architecture has the following merits: excellent accuracy results due to the accuracy studies for the finite word length; high speed operations owing to the high performance concurrent processing structure; and real-time response for 44.1 KHz sampling data.

AB - A high performance VLSI architecture is proposed for the 3D sound generation chip. A single 3D sound chip design reduces the cost and size of many audio systems. The proposed 3D sound VLSI architecture has the following merits: excellent accuracy results due to the accuracy studies for the finite word length; high speed operations owing to the high performance concurrent processing structure; and real-time response for 44.1 KHz sampling data.

UR - http://www.scopus.com/inward/record.url?scp=0031358019&partnerID=8YFLogxK

M3 - 會議論文

AN - SCOPUS:0031358019

SN - 0747-668X

SP - 296

EP - 297

JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

T2 - Proceedings of the 1997 16th International Conference on Consumer Electronics, ICCE

Y2 - 11 June 1997 through 13 June 1997

ER -

VLSI implementation of 3-D sound generator

Abstract

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