VLSI implementation of 3-D sound generator

An Nan Suen, Jhing Fa Wang, Jia Ching Wang

Research output: Contribution to journalConference articlepeer-review


A high performance VLSI architecture is proposed for the 3D sound generation chip. A single 3D sound chip design reduces the cost and size of many audio systems. The proposed 3D sound VLSI architecture has the following merits: excellent accuracy results due to the accuracy studies for the finite word length; high speed operations owing to the high performance concurrent processing structure; and real-time response for 44.1 KHz sampling data.

Original languageEnglish
Pages (from-to)296-297
Number of pages2
JournalDigest of Technical Papers - IEEE International Conference on Consumer Electronics
StatePublished - 1997
EventProceedings of the 1997 16th International Conference on Consumer Electronics, ICCE - Rosemont, IL, USA
Duration: 11 Jun 199713 Jun 1997


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