VLSI design of an SVM learning core on sequential minimal optimization algorithm

Ta Wen Kuan, Jhing Fa Wang, Jia Ching Wang, Po Chuan Lin, Gaung Hui Gu

Research output: Contribution to journalArticlepeer-review

55 Scopus citations

Abstract

The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array.

Original languageEnglish
Article number5713858
Pages (from-to)673-683
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number4
DOIs
StatePublished - Apr 2012

Keywords

  • Field-programmable gate array (FPGA)
  • VLSI design
  • sequential minimal optimization (SMO)
  • support vector machine (SVM)

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