VLSI design of a very low bit rate speech decoder

Jia Ching Wang; Jhing Fa Wang; Yun Fei Chao; Ming Chi Shi

VLSI design of a very low bit rate speech decoder

Jia Ching Wang, Jhing Fa Wang, Yun Fei Chao, Ming Chi Shi

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This study presents an FBLPC vocoder and an ASIC architecture for its decoding process. The FBLPC vocoder is based a forward-backward waveform prediction, and the required bit rate is approximately 1.2 kbps. Regarding the ASIC decoder, dedicated architectures are devised for the separate decoding modules. These architectures are then integrated through resource-sharing to achieve a cost effective design.

Original language	English
Title of host publication	Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
Editors	V.G. Oklobdzija
Pages	239-243
Number of pages	5
State	Published - 2005
Event	Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005 - Marina del Rey, CA, United States Duration: 24 Oct 2005 → 26 Oct 2005

Publication series

Name	Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

Conference

Conference	Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
Country/Territory	United States
City	Marina del Rey, CA
Period	24/10/05 → 26/10/05

Keywords

ASIC
LPC
LSP
Speech coding
VLSI
Vocoder

Cite this

@inproceedings{fd815f2de95b4ec784028bda04c9b2b5,

title = "VLSI design of a very low bit rate speech decoder",

abstract = "This study presents an FBLPC vocoder and an ASIC architecture for its decoding process. The FBLPC vocoder is based a forward-backward waveform prediction, and the required bit rate is approximately 1.2 kbps. Regarding the ASIC decoder, dedicated architectures are devised for the separate decoding modules. These architectures are then integrated through resource-sharing to achieve a cost effective design.",

keywords = "ASIC, LPC, LSP, Speech coding, VLSI, Vocoder",

author = "Wang, {Jia Ching} and Wang, {Jhing Fa} and Chao, {Yun Fei} and Shi, {Ming Chi}",

year = "2005",

language = "???core.languages.en_GB???",

isbn = "0889865094",

series = "Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005",

pages = "239--243",

editor = "V.G. Oklobdzija",

booktitle = "Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005",

note = "Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005 ; Conference date: 24-10-2005 Through 26-10-2005",

}

Wang, JC, Wang, JF, Chao, YF & Shi, MC 2005, VLSI design of a very low bit rate speech decoder. in VG Oklobdzija (ed.), Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005. Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005, pp. 239-243, Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005, Marina del Rey, CA, United States, 24/10/05.

VLSI design of a very low bit rate speech decoder. / Wang, Jia Ching; Wang, Jhing Fa; Chao, Yun Fei et al.
Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005. ed. / V.G. Oklobdzija. 2005. p. 239-243 (Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - VLSI design of a very low bit rate speech decoder

AU - Wang, Jia Ching

AU - Wang, Jhing Fa

AU - Chao, Yun Fei

AU - Shi, Ming Chi

PY - 2005

Y1 - 2005

N2 - This study presents an FBLPC vocoder and an ASIC architecture for its decoding process. The FBLPC vocoder is based a forward-backward waveform prediction, and the required bit rate is approximately 1.2 kbps. Regarding the ASIC decoder, dedicated architectures are devised for the separate decoding modules. These architectures are then integrated through resource-sharing to achieve a cost effective design.

AB - This study presents an FBLPC vocoder and an ASIC architecture for its decoding process. The FBLPC vocoder is based a forward-backward waveform prediction, and the required bit rate is approximately 1.2 kbps. Regarding the ASIC decoder, dedicated architectures are devised for the separate decoding modules. These architectures are then integrated through resource-sharing to achieve a cost effective design.

KW - ASIC

KW - LPC

KW - LSP

KW - Speech coding

KW - VLSI

KW - Vocoder

UR - http://www.scopus.com/inward/record.url?scp=33244493964&partnerID=8YFLogxK

M3 - 會議論文篇章

AN - SCOPUS:33244493964

SN - 0889865094

T3 - Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

SP - 239

EP - 243

BT - Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

A2 - Oklobdzija, V.G.

T2 - Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

Y2 - 24 October 2005 through 26 October 2005

ER -

VLSI design of a very low bit rate speech decoder

Abstract

Publication series

Conference

Keywords

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Cite this