VLSI architecture design for concatenative speech synthesizer

Li Ping Chu, Jia Ching Wang, Jhing Fa Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents a VLSI architecture for Mandarin speech synthesis. For the natural synthesized speech, subsyllable based synthesis units are recorded in advance. The synthesized speech is obtained by suitably concatenating the synthesis units. The TD-PSOLA (Time Domain Pitch Synchronous Overlap-and-Add) approach is used to perform the prosody modification. The proposed VLSI architecture includes two parts: the TD-PSOLA module and the synthesized pitch period generator. In the TD-PSOLA module, we also present a fast CORDIC architecture which is five times faster than the conventional method.

Original languageEnglish
Title of host publicationTENCON 2005 - 2005 IEEE Region 10 Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)0780393112, 9780780393110
DOIs
StatePublished - 2005
EventTENCON 2005 - 2005 IEEE Region 10 Conference - Melbourne, Australia
Duration: 21 Nov 200524 Nov 2005

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON
Volume2007
ISSN (Print)2159-3442
ISSN (Electronic)2159-3450

Conference

ConferenceTENCON 2005 - 2005 IEEE Region 10 Conference
Country/TerritoryAustralia
CityMelbourne
Period21/11/0524/11/05

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