VLSI architecture design for BNN speech recognition

Jia Ching Wang, Jhing Fa Wang, Fan Min Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we present the efficient VLSI architecture for the stand-alone application of the speech recognition system based on Bayesian neural network (BNN). Consider the recognition phase, the architecture of the Bayesian distance unit (BDU) is constructed based on one or multiple fundamental distance units. Template-serial and template-parallel architectures are both proposed to be associated with the BDU to perform the recognition procedure. In accordance with the number of the basic recognition units and the adopted BDU architecture, the choice is made between template-serial and template-parallel architectures so that the frame synchronous feature can be achieved in an efficient way.

Original languageEnglish
Title of host publicationProceedings of the IASTED International Conference on Signal Processing, Pattern Recognition, and Applications
EditorsM.H. Hamza
Pages200-204
Number of pages5
StatePublished - 2003
EventProceedings of the IASTED International Conference on Signal Processing, Pattern Recognition and Applications - Rhodes, Greece
Duration: 30 Jun 20032 Jul 2003

Publication series

NameProceedings of the IASTED International Conference on Signal Processing, Pattern Reconition, and Applications

Conference

ConferenceProceedings of the IASTED International Conference on Signal Processing, Pattern Recognition and Applications
Country/TerritoryGreece
CityRhodes
Period30/06/032/07/03

Keywords

  • Bayesian neural network
  • Speech recognition
  • VLSI

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