Vernier caliper and equivalent-signal sampling for built-in jitter measurement system

Shu Yu Jiang, Chan Wei Huang, Yu Lung Lo, Kuo Hsing Cheng

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 μm CMOS process. Furthermore these techniques are successfully verified in 14 ps circuit resolution and a 500*750 μm chip area for the 100-400 MHz measurement range.

Original languageEnglish
Pages (from-to)389-400
Number of pages12
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE92-A
Issue number2
DOIs
StatePublished - Feb 2009

Keywords

  • Auto focus
  • Built-in jitter measurement
  • Equivalent-signal sampling
  • Vernier caliper

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