Verification pattern generation for core-based design using port order fault model

Shing Wu Tung, Jing Yang Jou

Research output: Contribution to journalConference articlepeer-review

11 Scopus citations


The lack of information about core's internal structure is The designers must rely solely on the test set distributed by the core provider. Sometimes the stuck at fault (SAF) model and automatic test pattern generation (ATPG) are used to generate test vectors for those pre-defined blocks. However, a SAF test set could waste lots of time to verify the pre-verified internal structure of the cores. Therefore, in order to reduce the core-based design verification time, we should adopt the connectivity-based port order fault (POF) model instead of the stuck at fault model. In this paper, we compare the POF model with the SAF model and propose a method that the POF test set for functional verification can be generated by using the SAF-based ATPG tools with proper assignment of don't care terms in inputs.

Original languageEnglish
Pages (from-to)402-407
Number of pages6
JournalProceedings of the Asian Test Symposium
StatePublished - 1998
EventProceedings of the 1998 7th Asian Test Symposium - Singapore, Singapore
Duration: 2 Dec 19984 Dec 1998


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