Verification methodology for self-repairable memory systems

Jin Fu Li, Chun Hsien Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

With the nanometer-scale semiconductor technology, built-in self-repair (BISR) schemes are emerging techniques for improving the yield of embedded memories. A built-in self-repairable memory system typically consists of repairable memory cores, wrappers, built-in self-test (BIST) circuit, fuse group, and built-in redundancy-analyzer. This paper presents a system-level verification methodology for built-in self-repairable memory systems. The proposed verification methodology can verify the connectivity between the wrappers and self-repairable memories in a self-repairable memory system. Also, it can verify the wrapper misplaced design errors.

Original languageEnglish
Title of host publicationProceedings of the 15th Asian Test Symposium 2006
Pages109-114
Number of pages6
DOIs
StatePublished - 2006
Event15th Asian Test Symposium 2006 - Fukuoka, Japan
Duration: 20 Nov 200623 Nov 2006

Publication series

NameProceedings of the Asian Test Symposium
Volume2006
ISSN (Print)1081-7735

Conference

Conference15th Asian Test Symposium 2006
Country/TerritoryJapan
CityFukuoka
Period20/11/0623/11/06

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