Variability-tolerant binary content addressable memory cells

Sheng Ping Yong; Jin Fu Li; Yu Jen Huang

doi:10.1109/MTDT.2009.18

Variability-tolerant binary content addressable memory cells

Sheng Ping Yong, Jin Fu Li, Yu Jen Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Within-chip variability has become a serious problem in modern nano-scale technologies, which is particular true for semiconductor memory designs. This paper proposes four-types of variability-tolerant (VT) binary content addressable memory (BCAM) cells. The VT-BCAM cells are designed by separating the read port from the write port such that the sizing for read static noise margin (SNM) and write trip voltage (WTV) is decoupled. By reusing the comparison logic of a BCAM cell as the read port, moreover, only an additional transistor and a read wordline are needed. Experimental results show that in comparison with the typical BCAM cell the proposed variability-tolerant BCAM cells can provide about 0.655V increment of read SNM by paying about 13% additional cell area.

Original language	English
Title of host publication	Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Pages	44-49
Number of pages	6
DOIs	https://doi.org/10.1109/MTDT.2009.18
State	Published - 2009
Event	2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 - Hsinchu, Taiwan Duration: 31 Aug 2009 → 2 Sep 2009

Publication series

Name	Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Conference

Conference	2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Country/Territory	Taiwan
City	Hsinchu
Period	31/08/09 → 2/09/09

Access to Document

10.1109/MTDT.2009.18

Cite this

Yong, S. P., Li, J. F., & Huang, Y. J. (2009). Variability-tolerant binary content addressable memory cells. In Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 (pp. 44-49). Article 5279830 (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009). https://doi.org/10.1109/MTDT.2009.18

@inproceedings{7911c5378c1241ee9fb058e94dfaf71c,

title = "Variability-tolerant binary content addressable memory cells",

abstract = "Within-chip variability has become a serious problem in modern nano-scale technologies, which is particular true for semiconductor memory designs. This paper proposes four-types of variability-tolerant (VT) binary content addressable memory (BCAM) cells. The VT-BCAM cells are designed by separating the read port from the write port such that the sizing for read static noise margin (SNM) and write trip voltage (WTV) is decoupled. By reusing the comparison logic of a BCAM cell as the read port, moreover, only an additional transistor and a read wordline are needed. Experimental results show that in comparison with the typical BCAM cell the proposed variability-tolerant BCAM cells can provide about 0.655V increment of read SNM by paying about 13% additional cell area.",

author = "Yong, {Sheng Ping} and Li, {Jin Fu} and Huang, {Yu Jen}",

year = "2009",

doi = "10.1109/MTDT.2009.18",

language = "???core.languages.en_GB???",

isbn = "9780769537979",

series = "Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009",

pages = "44--49",

booktitle = "Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009",

note = "2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 ; Conference date: 31-08-2009 Through 02-09-2009",

}

Yong, SP, Li, JF & Huang, YJ 2009, Variability-tolerant binary content addressable memory cells. in Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009., 5279830, Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009, pp. 44-49, 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009, Hsinchu, Taiwan, 31/08/09. https://doi.org/10.1109/MTDT.2009.18

Variability-tolerant binary content addressable memory cells. / Yong, Sheng Ping; Li, Jin Fu; Huang, Yu Jen.
Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009. 2009. p. 44-49 5279830 (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Variability-tolerant binary content addressable memory cells

AU - Yong, Sheng Ping

AU - Li, Jin Fu

AU - Huang, Yu Jen

PY - 2009

Y1 - 2009

N2 - Within-chip variability has become a serious problem in modern nano-scale technologies, which is particular true for semiconductor memory designs. This paper proposes four-types of variability-tolerant (VT) binary content addressable memory (BCAM) cells. The VT-BCAM cells are designed by separating the read port from the write port such that the sizing for read static noise margin (SNM) and write trip voltage (WTV) is decoupled. By reusing the comparison logic of a BCAM cell as the read port, moreover, only an additional transistor and a read wordline are needed. Experimental results show that in comparison with the typical BCAM cell the proposed variability-tolerant BCAM cells can provide about 0.655V increment of read SNM by paying about 13% additional cell area.

AB - Within-chip variability has become a serious problem in modern nano-scale technologies, which is particular true for semiconductor memory designs. This paper proposes four-types of variability-tolerant (VT) binary content addressable memory (BCAM) cells. The VT-BCAM cells are designed by separating the read port from the write port such that the sizing for read static noise margin (SNM) and write trip voltage (WTV) is decoupled. By reusing the comparison logic of a BCAM cell as the read port, moreover, only an additional transistor and a read wordline are needed. Experimental results show that in comparison with the typical BCAM cell the proposed variability-tolerant BCAM cells can provide about 0.655V increment of read SNM by paying about 13% additional cell area.

UR - http://www.scopus.com/inward/record.url?scp=72349083313&partnerID=8YFLogxK

U2 - 10.1109/MTDT.2009.18

DO - 10.1109/MTDT.2009.18

M3 - 會議論文篇章

AN - SCOPUS:72349083313

SN - 9780769537979

T3 - Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

SP - 44

EP - 49

BT - Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

T2 - 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Y2 - 31 August 2009 through 2 September 2009

ER -

Variability-tolerant binary content addressable memory cells

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this