Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

Chung Huang Yeh, Jwu E. Chen, Chia Jui Chang, Tse Chia Huang

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technology and manufacturing technology, the testing capability of wafers is far behind the manufacturing capability of the semiconductor. Therefore, with the advancement in technology, the test yield loss caused by the tester inaccuracy has become an important problem. In this article, we propose an enhanced integrated circuit (IC) test scheme (ITS) that uses multiplex testing to improve test quality and test pass rate by retesting, and we rely on the cost evaluation mechanism to obtain the best test and the best profit. Furthermore, the International Roadmap for Devices and Systems (IRDS) 2017 data are used to estimate future test yield trends, and the results prove that the enhanced test scheme (ETS) can effectively estimate the best retest time to obtain the best test yield and the best profit.

Original languageEnglish
Article number1115
JournalElectronics (Switzerland)
Volume11
Issue number7
DOIs
StatePublished - 1 Apr 2022

Keywords

  • defect level
  • guardband test
  • manufacturing yield
  • test quality
  • threshold test

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