Two-Level logic minimization for low power

Jyh Mou Tseng Itri, Jing Yang Jou

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


In this paper we present a complete Boolean method for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates, and dynamic PLA implementations. We modify the espresso algorithm by adding our heuristics, which bias logic minimization toward lowering power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. The experimental results are promising.

Original languageEnglish
Pages (from-to)52-69
Number of pages18
JournalACM Transactions on Design Automation of Electronic Systems
Issue number1
StatePublished - 1999


  • Logic synthesis
  • Low power design
  • Programmable logic array
  • Two-level logic minimization


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