@inproceedings{7f59869dd1234787afedc8155a82d360,
title = "TRANS: A fast and memory-efficient path delay fault simulator",
abstract = "For path fault testing, simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits except c6288 for one million patterns, TRANS runs within 2.5 hours and 2.2 mega-bytes for each circuit. Comparing the experimental results with one of DAC'89, TRANS gets 85 times the gain of memory-speed product.",
author = "Lin, {Meng Chiy} and Chen, {Jwu E.} and Lee, {Chung Len}",
year = "1994",
language = "???core.languages.en_GB???",
isbn = "0818654112",
series = "Proceedings of the European Design and Test Conference",
publisher = "Publ by IEEE",
pages = "508--512",
editor = "Anon",
booktitle = "Proceedings of the European Design and Test Conference",
note = "Proceedings of the European Design and Test Conference ; Conference date: 28-02-1994 Through 03-03-1994",
}