Toward multi-gigabit wireless: Design of high-throughput MIMO detectors with hardware-efficient architecture

Meng Yuan Huang, Pei Yun Tsai

Research output: Contribution to journalArticlepeer-review

18 Scopus citations

Abstract

This paper presents a hardware-efficient architecture for 4×4 and 8×8 high-throughput MIMO detectors. The adopted non-constant K-best algorithm tends to keep more survival nodes in top search tree layers and reduce computational complexity in bottom layers as opposed to the conventional K-best algorithm. A pipelined architecture is used to generate one detection output per clock cycle, thus meeting multi-gigabit throughput requirements for advanced wireless communication systems. The proposed efficient folding scheme strikes a suitable balance between complexity and throughput. This paper also presents a discussion on the scalability of this architecture with respect to the setting of QAM size, K values, and antenna number. One 4×4 MIMO detector IC has been manufactured and one 8×8 MIMO detector layout has been realized, both in 90-nm CMOS technology. The 4×4 detector IC has 232 kilogates (KG). Its maximum measured throughput is 4.08 Gbps at 170-MHz operating frequency and 1.3-V core voltage. The 8×8 detector has 665 KG. Its post-layout simulation results show that it achieves 4.37-Gbps throughput at 182-MHz operating frequency and 0.9-V core voltage. Compared to earlier hard-output detectors, both implemented detectors demonstrate good normalized power and normalized hardware efficiencies.

Original languageEnglish
Article number6693747
Pages (from-to)613-624
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number2
DOIs
StatePublished - Feb 2014

Keywords

  • Folding
  • K-best
  • MIMO detector
  • VLSI
  • high throughput
  • multiple-input multiple-output (MIMO)
  • scalability

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