To verify manufacturing yield by testing

Mill Jer Wang, Jwu E. Chen, Yung Yuan Chen

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


The effect of test errors should be canceled while before test yield is used to analyze the manufacturing yield. Test errors can be alleviated from engineering run and production run stages. One of the more difficult aspect of yield modeling is the fact that defect density is generally not constant with time. In this paper, we study the flow of defect monitor used in production test. Based on the yield data obtained from engineering stage, the upper and lower bounds of chip yield are calculated after determining the variance of defect density and used to diagnose the results after wafer sort while in production. One ASIC product is used to validate this yield analysis procedure. This work can assist the ASIC design center to determine a manufacturing laboratory beginning the design and to control the chip area in the period of circuit design.

Original languageEnglish
Pages (from-to)385-390
Number of pages6
JournalProceedings of the Asian Test Symposium
StatePublished - 1994
EventProceedings of the 3rd Asian Test Symposium - Nara, Jpn
Duration: 15 Nov 199417 Nov 1994


Dive into the research topics of 'To verify manufacturing yield by testing'. Together they form a unique fingerprint.

Cite this