Timing-Driven Partial Scan

Jing Yang Jou, Kwang Ting Cheng

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


This partial scan approach reduces area overhead and performance degradation caused by test logic. Given an initial design that meets a target speed, the authors' algorithm selects a set of scan flip-flops that allows the circuit to meet performance requirements after the scan logic is added. If no such set exists, the algorithm selects a set that minimizes the total area increase caused by the scan logic and the subsequent performance optimization the circuit requires to meet target speed.

Original languageEnglish
Pages (from-to)52-59
Number of pages8
JournalIEEE Design and Test of Computers
Issue number4
StatePublished - 1995


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