The understanding of the trap induced variation in bulk tri-gate devices by a novel Random Trap Profiling (RTP) technique

H. M. Tsai, E. R. Hsieh, Steve S. Chung, C. H. Tsai, R. M. Huang, C. T. Tsai, C. W. Liang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the HC stress or NBTI-stress, induce the V th variations. To identify these traps, for the first time, a unique random trap profiling feasible for 3D device applications has been demonstrated on trigate devices. For such devices, the oxide traps are generated not only near the drain side but also on the sidewall, after hot carrier (HC) and NBTI stresses. More importantly, the Vth variation in pMOSFET under NBTI becomes much worse as a result of an additional surface roughness effect. This method provides us a valuable tool for the diagnosis of reliability in 3D devices (e.g., FinFET).

Original languageEnglish
Title of host publication2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
Pages189-190
Number of pages2
DOIs
StatePublished - 2012
Event2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
Duration: 12 Jun 201214 Jun 2012

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2012 Symposium on VLSI Technology, VLSIT 2012
Country/TerritoryUnited States
CityHonolulu, HI
Period12/06/1214/06/12

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