The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle

Wei Bin Yang; Shu Chang Kuo; Yuan Hua Chu; Kuo Hsing Cheng

doi:10.1109/ECCTD.2005.1523093

The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle

Wei Bin Yang
, Shu Chang Kuo
, Yuan Hua Chu
, Kuo Hsing Cheng

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V.

Original language	English
Title of host publication	Proceedings of the 2005 European Conference on Circuit Theory and Design
Pages	193-196
Number of pages	4
DOIs	https://doi.org/10.1109/ECCTD.2005.1523093
State	Published - 2005
Event	2005 European Conference on Circuit Theory and Design - Cork, Ireland Duration: 28 Aug 2005 → 2 Sep 2005

Publication series

Name	Proceedings of the 2005 European Conference on Circuit Theory and Design
Volume	3

Conference

Conference	2005 European Conference on Circuit Theory and Design
Country/Territory	Ireland
City	Cork
Period	28/08/05 → 2/09/05

Access to Document

10.1109/ECCTD.2005.1523093

Cite this

Yang, W. B., Kuo, S. C., Chu, Y. H., & Cheng, K. H. (2005). The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. In Proceedings of the 2005 European Conference on Circuit Theory and Design (pp. 193-196). Article 1523093 (Proceedings of the 2005 European Conference on Circuit Theory and Design; Vol. 3). https://doi.org/10.1109/ECCTD.2005.1523093

@inproceedings{fb623c17cc2045bc84540c5f23f72d20,

title = "The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50\% duty cycle",

abstract = "Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50\% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50\% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V.",

author = "Yang, \{Wei Bin\} and Kuo, \{Shu Chang\} and Chu, \{Yuan Hua\} and Cheng, \{Kuo Hsing\}",

year = "2005",

doi = "10.1109/ECCTD.2005.1523093",

language = "???core.languages.en\_GB???",

isbn = "0780390660",

series = "Proceedings of the 2005 European Conference on Circuit Theory and Design",

pages = "193--196",

booktitle = "Proceedings of the 2005 European Conference on Circuit Theory and Design",

note = "2005 European Conference on Circuit Theory and Design ; Conference date: 28-08-2005 Through 02-09-2005",

}

Yang, WB, Kuo, SC, Chu, YH & Cheng, KH 2005, The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. in Proceedings of the 2005 European Conference on Circuit Theory and Design., 1523093, Proceedings of the 2005 European Conference on Circuit Theory and Design, vol. 3, pp. 193-196, 2005 European Conference on Circuit Theory and Design, Cork, Ireland, 28/08/05. https://doi.org/10.1109/ECCTD.2005.1523093

The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. / Yang, Wei Bin; Kuo, Shu Chang; Chu, Yuan Hua et al.
Proceedings of the 2005 European Conference on Circuit Theory and Design. 2005. p. 193-196 1523093 (Proceedings of the 2005 European Conference on Circuit Theory and Design; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle

AU - Yang, Wei Bin

AU - Kuo, Shu Chang

AU - Chu, Yuan Hua

AU - Cheng, Kuo Hsing

PY - 2005

Y1 - 2005

N2 - Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V.

AB - Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V.

UR - https://www.scopus.com/pages/publications/33749007687

U2 - 10.1109/ECCTD.2005.1523093

DO - 10.1109/ECCTD.2005.1523093

M3 - 會議論文篇章

AN - SCOPUS:33749007687

SN - 0780390660

SN - 9780780390669

T3 - Proceedings of the 2005 European Conference on Circuit Theory and Design

SP - 193

EP - 196

BT - Proceedings of the 2005 European Conference on Circuit Theory and Design

T2 - 2005 European Conference on Circuit Theory and Design

Y2 - 28 August 2005 through 2 September 2005

ER -

The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle

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