The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle

Wei Bin Yang, Shu Chang Kuo, Yuan Hua Chu, Kuo Hsing Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V.

Original languageEnglish
Title of host publicationProceedings of the 2005 European Conference on Circuit Theory and Design
Pages193-196
Number of pages4
DOIs
StatePublished - 2005
Event2005 European Conference on Circuit Theory and Design - Cork, Ireland
Duration: 28 Aug 20052 Sep 2005

Publication series

NameProceedings of the 2005 European Conference on Circuit Theory and Design
Volume3

Conference

Conference2005 European Conference on Circuit Theory and Design
Country/TerritoryIreland
CityCork
Period28/08/052/09/05

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