The hardware design for a genetic algorithm accelerator for packet scheduling problems

Yang Han Lee, Yih Guang Jan, Yun Hsih Chou, Hsien Wei Tseng, Ming Hsueh Chuang, Shiann Tsong Sheu, Yue Ru Chuang, Jei Jung Shen, Chun Chieh Fan

Research output: Contribution to journalArticlepeer-review


In the basic genetic algorithm and its variations, they usually process the calculations in a sequential way so that the waiting time for every generation member awaited to be processed increases dramatically when the generation evolution continues. Consequently the algorithm converging rate becomes a serious problem when we try to apply the genetic algorithm in real time system operations such as in the packet scheduling and channels assignment in the fiber optic networks. We first propose in this paper a genetic algorithm accelerator which has the capability not only to accelerate the algorithm convergent rate but also to have its solution to reach the problem's optimum solution. Then we develop hardware blocks such as the blocks of Base Generator, Operation Selector, Delta Calculator, Duplicate Priority Encoder, Abort Priority Encoder and Next Generator, etc. to realize this proposed generic algorithm accelerator. Due to these hardware blocks realizations it will enhance the speed of the algorithm converging rate and make certain its convergent solution reaches the problem's optimum solution.

Original languageEnglish
Pages (from-to)165-174
Number of pages10
JournalTamkang Journal of Science and Engineering
Issue number2
StatePublished - Jun 2008


  • Abort priority encoder
  • Base generator
  • Delta calculator
  • Duplicate priority encoder
  • Genetic algorithm
  • Next generator
  • Operation selector
  • Packet scheduling


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