@inproceedings{dd2c299825a74cf6a94684057ead32e2,
title = "The Design of High Performance Si/SiGe-Based Tunneling FET: Strategies and Solutions",
abstract = "The strategy and solutions in the design of tunneling FET for low voltage/power applications will be addressed in this paper. First, the concept of a face-tunneling scheme to provide a sufficient improvement over the conventional point tunneling has been justified by an experiment. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, face-tunneling FET (f-TFET) can be enhanced in its Ion current. This work shows Ion of f-TFET with one-order magnitude Ion enhancement than that of point-TFET(control), and the longer the gate length is, the higher the Ion becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control. This can be better improved by careful treatment of a special design epi-channel, Next, further improvement of the TFET performance has been proposed by a further design of an improved epitaxial SiGe-based channel structure. The design is based on a raised-drain structure with further improvement on the Ion current and much lower S. S. down to 28mV/dec.",
author = "Chung, {Steve S.} and Hsieh, {E. R.} and Zhao, {Y. B.} and Lee, {J. W.} and Lee, {M. H.}",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018 ; Conference date: 06-06-2018 Through 08-06-2018",
year = "2018",
month = oct,
day = "9",
doi = "10.1109/EDSSC.2018.8487104",
language = "???core.languages.en_GB???",
series = "2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018",
}