The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond

E. R. Hsieh; C. W. Chang; C. C. Chuang; H. W. Chen; Steve S. Chung

doi:10.23919/VLSIC.2019.8778094

The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond

E. R. Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen, Steve S. Chung

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

A 4kb macro of One Time Programming (OTP) memory, implemented by a new breakdown, named dielectric fuse (dFuse) breakdown, has been realized on a foundry pure logic 28nm HKMG CMOS platform. The feature size of a unit cell is 1.5T per cell with 7.5F-2. The experimental results show that dFuse macro exhibits high programming (PGM) speed of 100ns at 4V, read time smaller than 10ns at 0.75V, and excellent data retention under one-month baking at 150°C. More importantly, the program voltage is weakly dependent on the environmental temperature, suitable for automotive applications. This OTP is also expected to be scalable to advanced node such as FinFET and provides an ideal and reliable solution for the storage purpose in IoT and 5G era.

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C208-C209
ISBN (Electronic)	9784863487185
DOIs	https://doi.org/10.23919/VLSIC.2019.8778094
State	Published - Jun 2019
Event	33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2019-June

Conference

Conference	33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

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10.23919/VLSIC.2019.8778094

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Hsieh, E. R., Chang, C. W., Chuang, C. C., Chen, H. W., & Chung, S. S. (2019). The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (pp. C208-C209). Article 8778094 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2019.8778094

Hsieh, E. R. ; Chang, C. W. ; Chuang, C. C. et al. / The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond. 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. pp. C208-C209 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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title = "The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond",

abstract = "A 4kb macro of One Time Programming (OTP) memory, implemented by a new breakdown, named dielectric fuse (dFuse) breakdown, has been realized on a foundry pure logic 28nm HKMG CMOS platform. The feature size of a unit cell is 1.5T per cell with 7.5F-2. The experimental results show that dFuse macro exhibits high programming (PGM) speed of 100ns at 4V, read time smaller than 10ns at 0.75V, and excellent data retention under one-month baking at 150°C. More importantly, the program voltage is weakly dependent on the environmental temperature, suitable for automotive applications. This OTP is also expected to be scalable to advanced node such as FinFET and provides an ideal and reliable solution for the storage purpose in IoT and 5G era.",

author = "Hsieh, {E. R.} and Chang, {C. W.} and Chuang, {C. C.} and Chen, {H. W.} and Chung, {Steve S.}",

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Hsieh, ER, Chang, CW, Chuang, CC, Chen, HW & Chung, SS 2019, The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers., 8778094, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. C208-C209, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIC.2019.8778094

The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond. / Hsieh, E. R.; Chang, C. W.; Chuang, C. C. et al.
2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. C208-C209 8778094 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chen, H. W.

AU - Chung, Steve S.

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AB - A 4kb macro of One Time Programming (OTP) memory, implemented by a new breakdown, named dielectric fuse (dFuse) breakdown, has been realized on a foundry pure logic 28nm HKMG CMOS platform. The feature size of a unit cell is 1.5T per cell with 7.5F-2. The experimental results show that dFuse macro exhibits high programming (PGM) speed of 100ns at 4V, read time smaller than 10ns at 0.75V, and excellent data retention under one-month baking at 150°C. More importantly, the program voltage is weakly dependent on the environmental temperature, suitable for automotive applications. This OTP is also expected to be scalable to advanced node such as FinFET and provides an ideal and reliable solution for the storage purpose in IoT and 5G era.

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Hsieh ER, Chang CW, Chuang CC, Chen HW, Chung SS. The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. C208-C209. 8778094. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2019.8778094

The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond

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