The cycle-efficient IDCT algorithm for H.264/SVC with DSP platform

Huang Chun Lin, Yu Hsuan Lee, Tsung Han Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, the cycle-efficient IDCT algorithm is proposed for H.264/SVC in DSP platform. Owing to the data structure of IDCT in H.264/SVC JSVM, the extra memory access seriously degrades the performance of DSP platform. To overcome it, the proposed algorithm mainly incorporates three techniques, data structure reordering, symmetrical-based scheduling and interleaving-parallelism technique. For each 4x4 IDCT, the proposed algorithm achieves only 20 cycles are consumed. With two spatial layers of 4CIF and CIF, the IDCT processing speed is accelerated as high as 18.6 times under 30 fps.

Original languageEnglish
Title of host publicationProceedings - 2009 IEEE International Conference on Multimedia and Expo, ICME 2009
Pages1114-1117
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE International Conference on Multimedia and Expo, ICME 2009 - New York, NY, United States
Duration: 28 Jun 20093 Jul 2009

Publication series

NameProceedings - 2009 IEEE International Conference on Multimedia and Expo, ICME 2009

Conference

Conference2009 IEEE International Conference on Multimedia and Expo, ICME 2009
Country/TerritoryUnited States
CityNew York, NY
Period28/06/093/07/09

Keywords

  • DSP platform
  • IDCT
  • Parallel processing
  • Scalable video coding

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