Testing of in-memory-computing 8T SRAMs

Tsai Ling Tsai; Jin Fu Li; Chun Lung Hsu; Chi Tien Sun

doi:10.1109/DFT.2019.8875487

Testing of in-memory-computing 8T SRAMs

Tsai Ling Tsai, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

26 Scopus citations

Abstract

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.

Original language	English
Title of host publication	2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728122601
DOIs	https://doi.org/10.1109/DFT.2019.8875487
State	Published - Oct 2019
Event	32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 - Noordwijk, Netherlands Duration: 2 Oct 2019 → 4 Oct 2019

Publication series

Name	2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019

Conference

Conference	32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
Country/Territory	Netherlands
City	Noordwijk
Period	2/10/19 → 4/10/19

Access to Document

10.1109/DFT.2019.8875487

Testing and Reliability-Enhancement Techniques for Stacked Memories(3/3)
Li, J.-F. (PI)
1/08/18 → 31/07/19
Project: Research
Testing of Emerging Nonvolatile-Based Memories for Iot(3/3)
Li, J.-F. (PI)
1/08/18 → 31/07/19
Project: Research

Cite this

Tsai, T. L., Li, J. F., Hsu, C. L., & Sun, C. T. (2019). Testing of in-memory-computing 8T SRAMs. In 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 Article 8875487 (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2019.8875487

Tsai, Tsai Ling ; Li, Jin Fu ; Hsu, Chun Lung et al. / Testing of in-memory-computing 8T SRAMs. 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019).

@inproceedings{3faf9794baca4ccc93fdac8ba95f3445,

title = "Testing of in-memory-computing 8T SRAMs",

abstract = "To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.",

author = "Tsai, {Tsai Ling} and Li, {Jin Fu} and Hsu, {Chun Lung} and Sun, {Chi Tien}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 ; Conference date: 02-10-2019 Through 04-10-2019",

year = "2019",

month = oct,

doi = "10.1109/DFT.2019.8875487",

language = "???core.languages.en_GB???",

series = "2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019",

}

Tsai, TL, Li, JF , Hsu, CL & Sun, CT 2019, Testing of in-memory-computing 8T SRAMs. in 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019., 8875487, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019, Institute of Electrical and Electronics Engineers Inc., 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019, Noordwijk, Netherlands, 2/10/19. https://doi.org/10.1109/DFT.2019.8875487

Testing of in-memory-computing 8T SRAMs. / Tsai, Tsai Ling; Li, Jin Fu ; Hsu, Chun Lung et al.
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8875487 (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Testing of in-memory-computing 8T SRAMs

AU - Tsai, Tsai Ling

AU - Li, Jin Fu

AU - Hsu, Chun Lung

AU - Sun, Chi Tien

PY - 2019/10

Y1 - 2019/10

N2 - To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.

AB - To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.

UR - http://www.scopus.com/inward/record.url?scp=85074431239&partnerID=8YFLogxK

U2 - 10.1109/DFT.2019.8875487

DO - 10.1109/DFT.2019.8875487

M3 - 會議論文篇章

AN - SCOPUS:85074431239

T3 - 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019

BT - 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019

Y2 - 2 October 2019 through 4 October 2019

ER -

Tsai TL, Li JF , Hsu CL, Sun CT. Testing of in-memory-computing 8T SRAMs. In 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8875487. (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019). doi: 10.1109/DFT.2019.8875487

Testing of in-memory-computing 8T SRAMs

Abstract

Publication series

Conference

Access to Document

Fingerprint

Projects

Testing and Reliability-Enhancement Techniques for Stacked Memories(3/3)

Testing of Emerging Nonvolatile-Based Memories for Iot(3/3)

Cite this