Testing of in-memory-computing 8T SRAMs

Tsai Ling Tsai, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.

Original languageEnglish
Title of host publication2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728122601
DOIs
StatePublished - Oct 2019
Event32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 - Noordwijk, Netherlands
Duration: 2 Oct 20194 Oct 2019

Publication series

Name2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019

Conference

Conference32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
Country/TerritoryNetherlands
CityNoordwijk
Period2/10/194/10/19

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