Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability

Jin Fu Li

doi:10.1109/DFT59622.2023.10313537

Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability

Jin Fu Li

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Computing-in memories (CIMs) support memory and computing functions. The operations of computing function are much different from the read/write operations of conventional memories, e.g., multiple wordlines are activated, specific sensing methods, and so on. Those cause that the CIM has computing faults. Conventional march tests for memories cannot cover the computing faults and new test algorithms are needed. In this embedded tutorial, therefore, we introduce fault modeling and test development methods for CIMs with logic operations. Furthermore, we will provide perspectives on the design-for-testability techniques for CIMs as well.

Original language	English
Title of host publication	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Editors	Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350315004
DOIs	https://doi.org/10.1109/DFT59622.2023.10313537
State	Published - 2023
Event	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 - Juan-Les-Pins, France Duration: 3 Oct 2023 → 5 Oct 2023

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
ISSN (Print)	2576-1501
ISSN (Electronic)	2765-933X

Conference

Conference	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Country/Territory	France
City	Juan-Les-Pins
Period	3/10/23 → 5/10/23

Keywords

Computing-in memory
design-for-testability
faults
test algorithm
testing

Access to Document

10.1109/DFT59622.2023.10313537

運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一：運算記憶體之測試策略與自動化技術(3/3)
Li, J.-F. (PI)
1/08/25 → 31/07/26
Project: Research

Cite this

Li, J. F. (2023). Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. In L. Cassano, M. Psarakis, M. Traiola, & A. Bosio (Eds.), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT59622.2023.10313537

Li, Jin Fu. / Testing of Computing-In Memories : Faults, Test Algorithms, and Design-for-Testability. 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. editor / Luca Cassano ; Mihalis Psarakis ; Marcello Traiola ; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

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abstract = "Computing-in memories (CIMs) support memory and computing functions. The operations of computing function are much different from the read/write operations of conventional memories, e.g., multiple wordlines are activated, specific sensing methods, and so on. Those cause that the CIM has computing faults. Conventional march tests for memories cannot cover the computing faults and new test algorithms are needed. In this embedded tutorial, therefore, we introduce fault modeling and test development methods for CIMs with logic operations. Furthermore, we will provide perspectives on the design-for-testability techniques for CIMs as well.",

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Li, JF 2023, Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. in L Cassano, M Psarakis, M Traiola & A Bosio (eds), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, Institute of Electrical and Electronics Engineers Inc., 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, 3/10/23. https://doi.org/10.1109/DFT59622.2023.10313537

Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. / Li, Jin Fu.
36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. ed. / Luca Cassano; Mihalis Psarakis; Marcello Traiola; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Computing-in memories (CIMs) support memory and computing functions. The operations of computing function are much different from the read/write operations of conventional memories, e.g., multiple wordlines are activated, specific sensing methods, and so on. Those cause that the CIM has computing faults. Conventional march tests for memories cannot cover the computing faults and new test algorithms are needed. In this embedded tutorial, therefore, we introduce fault modeling and test development methods for CIMs with logic operations. Furthermore, we will provide perspectives on the design-for-testability techniques for CIMs as well.

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Li JF. Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. In Cassano L, Psarakis M, Traiola M, Bosio A, editors, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT59622.2023.10313537

Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability

Abstract

Publication series

Conference

Keywords

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Projects

運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一：運算記憶體之測試策略與自動化技術(3/3)

Cite this