Testing crosstalk faults of data and address buses in embedded RAMs

Jiunn Der Yu, Jin Fu Li, Tsu Wei Tseng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Random access memories (RAMs) have many long parallel wires which incur a greater probability for excessive crosstalk coupling effect. This paper presents a test algorithm for detecting crosstalk faults of address and data buses in RAMs. The test algorithm requires 12n+2m+2 Read/Write operations to cover 100% crosstalk faults for a RAM with m-bit addresses, n-bit data inputs/outputs. A BIST supporting March-CW and the proposed test is also implemented. Experimental results show that the area cost of the BIST is only about 3.1% for an 8K× 16-bit RAM based on TSMC 0.18μm standard cell library.

Original languageEnglish
Title of host publication2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
StatePublished - 2007
Event2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan
Duration: 25 Apr 200727 Apr 2007

Publication series

Name2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
Country/TerritoryTaiwan
CityHsinchu
Period25/04/0727/04/07

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