Testing comparison faults of ternary content addressable memories with asymmetric cells

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4 Scopus citations

Abstract

Ternary content addressable memory (TCAM) is one key component in the dedicated hardware modulars for high-performance networking applications. Symmetric and asymmetric cells are two widely used cell structures in TCAMs. An asymmetric cell consists of a binary content addressable memory (BCAM) bit and a mask bit. This paper proposes two march-like test algorithms, THit and TPAE, to cover the comparison faults of the BCAM cell and the comparison logic faults of the masking cell. THit requires 7N Write operations and (3N+2B) Compare operations to cover the comparison faults of an N × B-bit TCAM with Hit output only. TPAE requires 4N Write operations and (3N+2B) Compare operations to cover the comparison faults of an V × B-bit TCAM with priority address encoder (PAE) output.

Original languageEnglish
Title of host publicationProceedings of the 16th Asian Test Symposium, ATS 2007
Pages501-506
Number of pages6
DOIs
StatePublished - 2007
Event16th Asian Test Symposium, ATS 2007 - Beijing, China
Duration: 8 Oct 200711 Oct 2007

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Conference

Conference16th Asian Test Symposium, ATS 2007
Country/TerritoryChina
CityBeijing
Period8/10/0711/10/07

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