Testing comparison and delay faults of TCAMs with asymmetric cells

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10 Scopus citations

Abstract

Ternary content addressable memory (TCAM) is one key component in high-performance networking applications. An asymmetric TCAM cell consists of a binary content addressable memory (BCAM) bit and a mask bit. In this paper, we analyze comparison faults of the asymmetric TCAM cell based on BCAM comparison faults. Also, two delay faults for covering delay defects in the comparison circuits of a TCAM are proposed. Then two march-like test algorithms T H and TPAEare proposed to cover the comparison faults and delay faults of the comparison circuits in TCAMs with asymmetric cells. The test algorithm TH requires 7NWrite operations and (3N+2B) Compare operations to cover the comparison faults of an N × B-bit TCAM with Hit output only; and the test algorithm TPAE requires 4N Write operations and 3N+2B Compare operations to cover the comparison faults of an N × B-bit TCAM with priority address encoder (PAE) output.

Original languageEnglish
Article number5299103
Pages (from-to)912-920
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume18
Issue number6
DOIs
StatePublished - Jun 2010

Keywords

  • Asymmetric ternary content addressable memory (TCAM) cell
  • Comparison faults
  • Delay faults
  • March tests
  • Memory testing
  • TCAM

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