Testable PLA design with low overhead and ease of test generation

Jing Yang Jou

Testable PLA design with low overhead and ease of test generation

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The author presents a hybrid programmable-logic array (PLA) design-for-testability technique that requires negligible hardware overhead and still preserves the property of ease of test generation. The key idea is to further utilize the 'don't care' assignment by introducing the control of both true and complement bits of some inputs to meet the requirement of distance-2 test sets. This approach is applied to the BARNEW PLA, and results support the claim that the hardware overhead of this technique is negligible and the ease of test generation is preserved.

Original language	English
Title of host publication	1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc
Publisher	Publ by IEEE
Pages	450-453
Number of pages	4
ISBN (Print)	0818608722
State	Published - 1988

Publication series

Name	1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc

Cite this

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AB - The author presents a hybrid programmable-logic array (PLA) design-for-testability technique that requires negligible hardware overhead and still preserves the property of ease of test generation. The key idea is to further utilize the 'don't care' assignment by introducing the control of both true and complement bits of some inputs to meet the requirement of distance-2 test sets. This approach is applied to the BARNEW PLA, and results support the claim that the hardware overhead of this technique is negligible and the ease of test generation is preserved.

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BT - 1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc

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ER -

Testable PLA design with low overhead and ease of test generation

Abstract

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