Skip to main navigation
Skip to search
Skip to main content
National Central University Home
Help & FAQ
English
中文
Home
Scholar Profiles
Research units
Projects
Research output
Datasets
Prizes
Activities
Press/Media
Impacts
Search by expertise, name or affiliation
Testable and fault tolerant design for FFT networks
Jin Fu Li
, Cheng Wen Wu
Department of Electrical Engineering
Research output
:
Contribution to journal
›
Conference article
›
peer-review
3
Scopus citations
Overview
Fingerprint
Fingerprint
Dive into the research topics of 'Testable and fault tolerant design for FFT networks'. Together they form a unique fingerprint.
Sort by
Weight
Alphabetically
Keyphrases
Fast Fourier Transform
100%
Transform Network
100%
Fault-tolerant Design
100%
Test Pattern
20%
Low Computational Complexity
20%
16-bit
20%
Hardware Overhead
20%
Reconfiguration
20%
Combinational
20%
Stuck-at
20%
Cell Design
20%
Subtract
20%
Network Size
20%
Specialized Cell
20%
High Reliability
20%
Bit Level
20%
C-testability
20%
Computer Science
Fault Tolerant
100%
Fast Fourier Transform
100%
Hardware Overhead
40%
Reconfiguration
20%
High Reliability
20%
Engineering
Fast Fourier Transform
100%
Hardware Overhead
40%
Interconnects
20%
Reconfiguration
20%
Cell Design
20%
Bit Number
20%