Testable and fault tolerant design for FFT networks

Jin Fu Li, Cheng Wen Wu

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations


We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead - only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low - about 4% for 16-bit numbers regardless of the FFT network size.

Original languageEnglish
Pages (from-to)201-209
Number of pages9
JournalIEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
StatePublished - 1999
EventProceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99) - Albueqeurque, NM, USA
Duration: 1 Nov 19993 Nov 1999


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