Testability exploration of 3-D RAMs and CAMs

Yu Jen Huang, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations


Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable memories (CAMs) in the phase of testing of stacked 3-D ICs with functional faults. Analysis results show that the 3-D CAMs and RAMs can be tested with lower test complexity than the 2-D ones. Furthermore, simple design-for-testability (DFT) methods are proposed to reduce the test complexity of 3-D RAMs and CAMs further.

Original languageEnglish
Title of host publicationProceedings of the 18th Asian Test Symposium, ATS 2009
Number of pages6
StatePublished - 2009
Event18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan
Duration: 23 Nov 200926 Nov 2009

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference18th Asian Test Symposium, ATS 2009


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