@inproceedings{8ad8d7caea724eb98cc1284a57cb1492,
title = "Testability exploration of 3-D RAMs and CAMs",
abstract = "Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable memories (CAMs) in the phase of testing of stacked 3-D ICs with functional faults. Analysis results show that the 3-D CAMs and RAMs can be tested with lower test complexity than the 2-D ones. Furthermore, simple design-for-testability (DFT) methods are proposed to reduce the test complexity of 3-D RAMs and CAMs further.",
author = "Huang, {Yu Jen} and Li, {Jin Fu}",
year = "2009",
doi = "10.1109/ATS.2009.59",
language = "???core.languages.en_GB???",
isbn = "9780769538648",
series = "Proceedings of the Asian Test Symposium",
pages = "397--402",
booktitle = "Proceedings of the 18th Asian Test Symposium, ATS 2009",
note = "18th Asian Test Symposium, ATS 2009 ; Conference date: 23-11-2009 Through 26-11-2009",
}