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Test yield and quality analysis models of chips
Chung Huang Yeh, Jwu E. Chen
Department of Electrical Engineering
Research output
:
Contribution to journal
›
Article
›
peer-review
8
Scopus citations
Overview
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Keyphrases
Quality Analysis
100%
Testing Model
100%
Digital Circuits
100%
Test Yield
100%
Test Quality
100%
Yield Analysis
100%
Integrated Circuit Testing
66%
Accuracy Requirements
33%
Statistical Simulation Method
33%
International Technology Roadmap for Semiconductors
33%
Multiple Parameters
33%
Integrated chip
33%
Functional Test
33%
Manufacturability
33%
Integrated Circuit Manufacturing
33%
Manufacturing Parameters
33%
Chip Fabrication
33%
On-chip Testing
33%
Yield Quality
33%
At-speed
33%
Semiconductor Product
33%
Testing Parameters
33%
Quality Control Tests
33%
Integrated Circuit (IC) Testing
33%
Engineering
Digital Integrated Circuits
100%
Integrated Circuit Testing
66%
Simulated Result
33%
Normal Distribution
33%
Quality Control
33%
Statistical Simulation Method
33%
Manufacturability
33%
Functional Test
33%
Integrated Circuit
33%
Material Science
Electronic Circuit
100%