Test yield and quality analysis models of chips

In this work, we utilized a digital integrated-circuit (IC) testing model (DITM), based on a statistical simulation method, to evaluate the test yield and test quality of semiconductor products. A circuit or chip has multiple parameters and the relationships among these parameters at different levels are complicated. To simply express numerous and complex interrelated IC or chip manufacturing and testing parameters, we assumed a normal distribution of manufacturability and then standardized and related all other parameters. On applying the Digital integrated circuit testing model (DITM) to data on Accuracy Requirements in At-Speed Functional Test and International technology roadmap for semiconductors (ITRS Roadmap), the simulated results clearly indicated that when the threshold value of a quality control test is determined, the DITM can accurately and effectively predict future Y_t (Test Yield).