Test cost optimization technique for the pre-bond test of 3D ICs

Yong Xiao Chen, Yu Jen Huang, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.

Original languageEnglish
Title of host publicationProceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012
Pages102-107
Number of pages6
DOIs
StatePublished - 2012
Event2012 30th IEEE VLSI Test Symposium, VTS 2012 - Hyatt Maui, HI, United States
Duration: 23 Apr 201226 Apr 2012

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference2012 30th IEEE VLSI Test Symposium, VTS 2012
Country/TerritoryUnited States
CityHyatt Maui, HI
Period23/04/1226/04/12

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