Test and repair scheduling for built-in self-repair RAMs in SOCs

Chih Sheng Hou, Jin Fu Li, Che Wei Chou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Built-in self-repair (BISR) is one promising approach for improving the yield of memory cores in an system-on-chip (SOC). This paper presents a test scheduling approach for BISR memory cores under the constraint of maximum power consumption. An efficient test scheduling algorithm based on the early-abort probability is proposed. Experimental results show that the scheduled results of the proposed algorithm have lower expected test time in comparison with the previous work. For ITC'02 benchmarks, for example, about 10.7% average reduction ratio of expected test time can be achieved by the proposed algorithm.

Original languageEnglish
Title of host publicationProceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010
Pages3-7
Number of pages5
DOIs
StatePublished - 2010
Event5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010 - Ho Chi Minh City, Viet Nam
Duration: 13 Jan 201015 Jan 2010

Publication series

NameProceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010

Conference

Conference5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010
Country/TerritoryViet Nam
CityHo Chi Minh City
Period13/01/1015/01/10

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