System level integration methodology for MPEG-2 audio decoder with embedded RISC core

Tsung Han Tsai; Liang Gee Chen; Ren Jr Wu

System level integration methodology for MPEG-2 audio decoder with embedded RISC core

Tsung Han Tsai, Liang Gee Chen, Ren Jr Wu

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. Based on standard cell design technique, the chip size is 6.4 × 6.4 mm ², and the tested chip can run at maximum 43.5 MHz clock rate.

Original language	English
Pages (from-to)	46-49
Number of pages	4
Journal	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
State	Published - 1999
Event	Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan Duration: 7 Jun 1999 → 10 Jun 1999

Cite this

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title = "System level integration methodology for MPEG-2 audio decoder with embedded RISC core",

abstract = "MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. Based on standard cell design technique, the chip size is 6.4 × 6.4 mm 2, and the tested chip can run at maximum 43.5 MHz clock rate.",

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AB - MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. Based on standard cell design technique, the chip size is 6.4 × 6.4 mm 2, and the tested chip can run at maximum 43.5 MHz clock rate.

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M3 - 會議論文

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JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

T2 - Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications

Y2 - 7 June 1999 through 10 June 1999

ER -

System level integration methodology for MPEG-2 audio decoder with embedded RISC core

Abstract

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